return RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD);
case RTE_CRYPTODEV_SNOW3G_PMD:
return RTE_STR(CRYPTODEV_NAME_SNOW3G_PMD);
+ case RTE_CRYPTODEV_DPAA2_SEC_PMD:
+ return RTE_STR(CRYPTODEV_NAME_DPAA2_SEC_PMD);
default:
return "";
}
#endif
nb_devs = rte_cryptodev_count_devtype(RTE_CRYPTODEV_AESNI_MB_PMD);
if (nb_devs < 1) {
- ret = rte_eal_vdev_init(
+ ret = rte_vdev_init(
RTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD), NULL);
TEST_ASSERT(ret == 0,
#endif
nb_devs = rte_cryptodev_count_devtype(RTE_CRYPTODEV_AESNI_GCM_PMD);
if (nb_devs < 1) {
- ret = rte_eal_vdev_init(
+ ret = rte_vdev_init(
RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD), NULL);
TEST_ASSERT(ret == 0,
#endif
nb_devs = rte_cryptodev_count_devtype(RTE_CRYPTODEV_SNOW3G_PMD);
if (nb_devs < 1) {
- ret = rte_eal_vdev_init(
+ ret = rte_vdev_init(
RTE_STR(CRYPTODEV_NAME_SNOW3G_PMD), NULL);
TEST_ASSERT(ret == 0,
nb_devs = rte_cryptodev_count_devtype(
RTE_CRYPTODEV_OPENSSL_PMD);
if (nb_devs < 1) {
- ret = rte_eal_vdev_init(
+ ret = rte_vdev_init(
RTE_STR(CRYPTODEV_NAME_OPENSSL_PMD),
NULL);
nb_devs = rte_cryptodev_count_devtype(
RTE_CRYPTODEV_ARMV8_PMD);
if (nb_devs < 1) {
- ret = rte_eal_vdev_init(
+ ret = rte_vdev_init(
RTE_STR(CRYPTODEV_NAME_ARMV8_PMD),
NULL);
}
};
+static struct unit_test_suite cryptodev_dpaa2_sec_testsuite = {
+ .suite_name = "Crypto Device DPAA2_SEC Unit Test Suite",
+ .setup = testsuite_setup,
+ .teardown = testsuite_teardown,
+ .unit_test_cases = {
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_perf_aes_cbc_encrypt_digest_vary_pkt_size),
+ TEST_CASES_END() /**< NULL terminate unit test array */
+ }
+};
+
static struct unit_test_suite cryptodev_gcm_testsuite = {
.suite_name = "Crypto Device AESNI GCM Unit Test Suite",
.setup = testsuite_setup,
return unit_test_suite_runner(&cryptodev_armv8_testsuite);
}
+static int
+perftest_dpaa2_sec_cryptodev(void)
+{
+ gbl_cryptodev_perftest_devtype = RTE_CRYPTODEV_DPAA2_SEC_PMD;
+
+ return unit_test_suite_runner(&cryptodev_dpaa2_sec_testsuite);
+}
+
REGISTER_TEST_COMMAND(cryptodev_aesni_mb_perftest, perftest_aesni_mb_cryptodev);
REGISTER_TEST_COMMAND(cryptodev_qat_perftest, perftest_qat_cryptodev);
REGISTER_TEST_COMMAND(cryptodev_sw_snow3g_perftest, perftest_sw_snow3g_cryptodev);
perftest_qat_continual_cryptodev);
REGISTER_TEST_COMMAND(cryptodev_sw_armv8_perftest,
perftest_sw_armv8_cryptodev);
+REGISTER_TEST_COMMAND(cryptodev_dpaa2_sec_perftest,
+ perftest_dpaa2_sec_cryptodev);