common/cnxk: align NPA stack to ROC cache line size
authorAshwin Sekhar T K <asekhar@marvell.com>
Fri, 17 Sep 2021 11:23:09 +0000 (16:53 +0530)
committerJerin Jacob <jerinj@marvell.com>
Tue, 21 Sep 2021 09:08:55 +0000 (11:08 +0200)
commit14a4e2844b10540f4d49e806f6e9e8871bbdeb26
tree648d5978f87b8a7c6304bcc15671ed767fd68755
parent9eb5cb3b11cc97e8e0c61ee216bd586b4793335f
common/cnxk: align NPA stack to ROC cache line size

Network Pool accelerator (NPA) is part of ROC (Rest Of Chip). So
NPA structures should be aligned to ROC Cache line size and not
CPU cache line size.

Non alignment of NPA stack to ROC cache line will result in
undefined runtime NPA behaviour.

Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
Cc: stable@dpdk.org
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
drivers/common/cnxk/roc_npa.c