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(parent: 3c2ddbd) | patch
net/mlx5: match Rx completion entry size to cacheline
authorYongseok Koh <yskoh@mellanox.com>
Mon, 9 Oct 2017 18:46:58 +0000 (11:46 -0700)
committerFerruh Yigit <ferruh.yigit@intel.com>
Thu, 12 Oct 2017 00:36:58 +0000 (01:36 +0100)
commit161b93e5e7d0482c0d7e77603c2406acdfc94088
tree465cee66e80df42e08829482a881ece32cecc8a6tree | snapshot
parent3c2ddbd413e34698b66df65a57b0c760ffe0b3d6commit | diff
net/mlx5: match Rx completion entry size to cacheline

The size of Rx completion entry should match the size of a cacheline.
This is already reflected in struct mlx5_cqe by adding 64bytes padding
if a cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
drivers/net/mlx5/mlx5.c diff | blob | history
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