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(parent: ed57d08) | patch
config: align mempool elements to 128 bytes on CN10K
authorPavan Nikhilesh <pbhagavatula@marvell.com>
Mon, 13 Dec 2021 11:06:14 +0000 (16:36 +0530)
committerThomas Monjalon <thomas@monjalon.net>
Sat, 12 Feb 2022 14:13:24 +0000 (15:13 +0100)
commit3e97fa671dee32ea2689eb18f868d9086613cc1b
treefb1afbd1bb52a46d6afceadf051c55a3f4e0f15etree | snapshot
parented57d08dfd4402a214fd60f1cd25faf9a5b3b2c3commit | diff
config: align mempool elements to 128 bytes on CN10K

Mempool elements are by default aligned to CACHELINE_SIZE.
In CN10K cacheline size is 64B but the RoC requires buffers to be
aligned to 128B.
Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
128 bytes.

Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
config/arm/meson.build diff | blob | history
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