net/i40e: relax barrier in Tx for NEON
authorGavin Hu <gavin.hu@arm.com>
Mon, 13 Apr 2020 16:40:24 +0000 (00:40 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 21 Apr 2020 11:57:08 +0000 (13:57 +0200)
commit6b50c489a3bb1d82e2549ae2f1e2c46961572c27
treec1a79dbec5210011eb94b992dd0607b5e2b2388d
parent746664d546fb3ef76ad8b9c731d296802495319c
net/i40e: relax barrier in Tx for NEON

To keep ordering of mixed accesses, 'DMB OSH' is sufficient.
'DSB' inside the I40E_PCI_REG_WRITE is overkill.[1]

This patch fixes by replacing with just sufficient barriers in the
normal PMD and vPMD.

It showed 7% performance uplift on ThunderX2 and 4% on Arm N1SDP.
The test case is the RFC2544 zero-loss test running testpmd.

[1] http://inbox.dpdk.org/dev/CALBAE1M-ezVWCjqCZDBw+MMDEC4O9
qf0Kpn89EMdGDajepKoZQ@mail.gmail.com

Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
drivers/net/i40e/i40e_rxtx_vec_neon.c