common/octeontx2: support C0 silicon version
authorNithin Dabilpuram <ndabilpuram@marvell.com>
Mon, 13 Jan 2020 05:03:02 +0000 (10:33 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 17 Jan 2020 18:46:26 +0000 (19:46 +0100)
commit89fc6763b1c964b89bd3ac21f55d802f48d5f6b9
tree2687328ac2ffb51028a0628cd45126d35a748c9c
parente4373bf1b3f51715bf66e87c0134e2c217e4612c
common/octeontx2: support C0 silicon version

Avoid using PCI subsystem device id for SoC revision
identification and just use PCI revision id to support C0 silicon.
This patch also reduces SQB threshold to 70% to have
sufficient buffer before we overflow SQ.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
drivers/common/octeontx2/otx2_common.h
drivers/common/octeontx2/otx2_dev.h
drivers/net/octeontx2/otx2_ethdev.h