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(parent: 02fc224) | patch
net/e1000/base: avoid packet loss for non-1G
authorWenzhuo Lu <wenzhuo.lu@intel.com>
Wed, 23 Nov 2016 17:22:46 +0000 (12:22 -0500)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 17 Jan 2017 18:36:48 +0000 (19:36 +0100)
commit8cce758d693a414a8a783a32c754d01a904f5930
tree945e8ecc4831ff8bac78d3e304cecca513308865tree | snapshot
parent02fc2241b1599c00bc561e64c05f7a7d53672a8ecommit | diff
net/e1000/base: avoid packet loss for non-1G

To avoid packet loss, Phase Lock Loop (PLL) clock gate time needs to be
increased for non 1G speeds.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
drivers/net/e1000/base/e1000_ich8lan.c diff | blob | history
drivers/net/e1000/base/e1000_ich8lan.h diff | blob | history
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