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(parent: bfe9776) | patch
net/ixgbe: align register setting when RSC is disabled
authorWei Dai <wei.dai@intel.com>
Thu, 20 Apr 2017 03:06:06 +0000 (11:06 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 28 Apr 2017 12:46:17 +0000 (14:46 +0200)
commitb826efba6de491659c9c2025e42b1bf9df8d933c
tree31e66eea23034e8bf6e06994f9c14b077bf101d6tree | snapshot
parentbfe977683a75838209805dd64ae118d1b375e935commit | diff
net/ixgbe: align register setting when RSC is disabled

When Receive Side Coalescing (RSC) is not used, the RSC Disable
(RSC_DIS) filed of register Receive Filter Control Register (RFCTL)
should be set according to ixgbe datasheet.

Signed-off-by: Wei Dai <wei.dai@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
drivers/net/ixgbe/ixgbe_rxtx.c diff | blob | history
DPDK repo used for reviews