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(parent: e6d3c09) | patch
common/octeontx2: support CNF95xx SoC
authorNithin Dabilpuram <ndabilpuram@marvell.com>
Fri, 12 Jul 2019 09:25:54 +0000 (14:55 +0530)
committerThomas Monjalon <thomas@monjalon.net>
Sun, 14 Jul 2019 13:39:49 +0000 (15:39 +0200)
commitd1d823e7a8652b4df81ff4e0f47a38263618979c
treeea92a425f7dfcca21a8f0b2a5d684dd8953da090tree | snapshot
parente6d3c09282d88e904e4255a0c81e0c19a92217c1commit | diff
common/octeontx2: support CNF95xx SoC

Update platform support of CNF95xx in documentation and
also, update the HW cap based on PCI subsystem id and revision id.
This patch also changes HW capability handling to be based on
PCI Revision ID. PCI Revision ID contains a unique identifier
to identify chip, major and minor revisions.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
doc/guides/platform/octeontx2.rst diff | blob | history
drivers/common/octeontx2/otx2_common.h diff | blob | history
drivers/common/octeontx2/otx2_dev.c diff | blob | history
drivers/common/octeontx2/otx2_dev.h diff | blob | history
drivers/common/octeontx2/rte_common_octeontx2_version.map diff | blob | history
drivers/net/octeontx2/otx2_ethdev.c diff | blob | history
drivers/net/octeontx2/otx2_flow_ctrl.c diff | blob | history
drivers/net/octeontx2/otx2_tm.c diff | blob | history
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