author | Xiaoyun Li <xiaoyun.li@intel.com> | |
Fri, 8 Sep 2017 03:28:52 +0000 (11:28 +0800) | ||
committer | Ferruh Yigit <ferruh.yigit@intel.com> | |
Fri, 6 Oct 2017 00:49:49 +0000 (02:49 +0200) | ||
commit | d2654a6a929c78c9098bd3ebf9aba2267facc066 | |
tree | 1566664b63539038cbf07a652a1fbf032b46ebc3 | tree | snapshot |
parent | 1fe427fd08ee5f06d15abadd51a64846e8ebf9c5 | commit | diff |
mk/machine/atm/rte.vars.mk | [deleted file] | blob | history |
mk/machine/silvermont/rte.vars.mk | [new file with mode: 0644] | blob |