ring: remove split cacheline build setting
authorBruce Richardson <bruce.richardson@intel.com>
Wed, 29 Mar 2017 15:21:17 +0000 (16:21 +0100)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Wed, 29 Mar 2017 20:21:51 +0000 (22:21 +0200)
commitd9f0d3a1ffd4b66e75485cc8b63b9aedfbdfe8b0
treed934575114c6ee487ad4fde130b1e80795a4d330
parent05cc9fec458ca6fb316342246f4775591988088e
ring: remove split cacheline build setting

Users compiling DPDK should not need to know or care about the arrangement
of cachelines in the rte_ring structure.  Therefore just remove the build
option and set the structures to be always split. On platforms with 64B
cachelines, for improved performance use 128B rather than 64B alignment
since it stops the producer and consumer data being on adjacent cachelines.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
config/common_base
doc/guides/rel_notes/release_17_05.rst
lib/librte_ring/rte_ring.c
lib/librte_ring/rte_ring.h