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(parent: b4e5e60) | patch
e1000/base: fix reset of DH89XXCC SGMII
authorWenzhuo Lu <wenzhuo.lu@intel.com>
Fri, 16 Oct 2015 02:50:54 +0000 (10:50 +0800)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Tue, 27 Oct 2015 15:12:56 +0000 (16:12 +0100)
commite6c005f7114aeb84408949fa805a68c721a3c225
tree05b53f3829fa230552d31f963333eef75a8dce57tree | snapshot
parentb4e5e60cbe64415d1aae9fb0194df7fa34223a7fcommit | diff
e1000/base: fix reset of DH89XXCC SGMII

For DH89XXCC_SGMII, write flush leaves registers of this device trashed
(0xFFFFFFFF). Added check for this device.
Also, after both for Port SW Reset and Device Reset case, platform should
wait at least 3ms before reading any registers. Since waiting is
conditionally executed only for Device Reset - removed the condition.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
drivers/net/e1000/base/e1000_82575.c diff | blob | history
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