event/dlb2: add v2.5 sparse CQ mode

event/dlb2: add v2.5 sparse CQ mode

Update the low level HW functions responsible for
configuring sparse CQ mode, where each cache line
contains just one QE instead of 4.

The logic is very similar to what was done for v2.0,
but the new combined register map for v2.0 and v2.5
uses new register names and bit names.  Additionally,
new register access macros are used so that the code
can perform the correct action, based on the hardware.

Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>