Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
uint32_t board_type = 0;
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
uint32_t board_type = 0;
uint32_t port;
uint32_t pf;
uint32_t vf;
uint32_t port;
uint32_t pf;
uint32_t vf;
encp->enc_buftbl_limit = 0xFFFFFFFF;
encp->enc_buftbl_limit = 0xFFFFFFFF;
+ /* Get interrupt vector limits */
+ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
+ if (EFX_PCI_FUNCTION_IS_PF(encp))
+ goto fail9;
+
+ /* Ignore error (cannot query vector limits from a VF). */
+ base = 0;
+ nvec = 1024;
+ }
+ encp->enc_intr_vec_base = base;
+ encp->enc_intr_limit = nvec;
+
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)
if (rc != EACCES)
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)
if (rc != EACCES)
+fail10:
+ EFSYS_PROBE(fail10);
fail9:
EFSYS_PROBE(fail9);
fail8:
fail9:
EFSYS_PROBE(fail9);
fail8:
uint32_t mask;
uint32_t flags;
uint32_t sysclk, dpcpu_clk;
uint32_t mask;
uint32_t flags;
uint32_t sysclk, dpcpu_clk;
uint32_t bandwidth;
efx_rc_t rc;
uint32_t bandwidth;
efx_rc_t rc;
goto fail5;
encp->enc_privilege_mask = mask;
goto fail5;
encp->enc_privilege_mask = mask;
- /* Get interrupt vector limits */
- if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail6;
-
- /* Ignore error (cannot query vector limits from a VF). */
- base = 0;
- nvec = 1024;
- }
- encp->enc_intr_vec_base = base;
- encp->enc_intr_limit = nvec;
-
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
/* All Huntington devices have a PCIe Gen3, 8 lane connector */
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
/* All Huntington devices have a PCIe Gen3, 8 lane connector */
-fail7:
- EFSYS_PROBE(fail7);
fail6:
EFSYS_PROBE(fail6);
fail5:
fail6:
EFSYS_PROBE(fail6);
fail5:
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t mask;
uint32_t sysclk, dpcpu_clk;
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t mask;
uint32_t sysclk, dpcpu_clk;
uint32_t end_padding;
uint32_t bandwidth;
uint32_t vi_window_shift;
uint32_t end_padding;
uint32_t bandwidth;
uint32_t vi_window_shift;
goto fail5;
encp->enc_privilege_mask = mask;
goto fail5;
encp->enc_privilege_mask = mask;
- /* Get interrupt vector limits */
- if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail6;
-
- /* Ignore error (cannot query vector limits from a VF). */
- base = 0;
- nvec = 1024;
- }
- encp->enc_intr_vec_base = base;
- encp->enc_intr_limit = nvec;
-
/*
* Medford2 stores a single global copy of VPD, not per-PF as on
* Huntington.
/*
* Medford2 stores a single global copy of VPD, not per-PF as on
* Huntington.
rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail7:
- EFSYS_PROBE(fail7);
fail6:
EFSYS_PROBE(fail6);
fail5:
fail6:
EFSYS_PROBE(fail6);
fail5:
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t mask;
uint32_t sysclk, dpcpu_clk;
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t mask;
uint32_t sysclk, dpcpu_clk;
uint32_t end_padding;
uint32_t bandwidth;
efx_rc_t rc;
uint32_t end_padding;
uint32_t bandwidth;
efx_rc_t rc;
goto fail4;
encp->enc_privilege_mask = mask;
goto fail4;
encp->enc_privilege_mask = mask;
- /* Get interrupt vector limits */
- if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail5;
-
- /* Ignore error (cannot query vector limits from a VF). */
- base = 0;
- nvec = 1024;
- }
- encp->enc_intr_vec_base = base;
- encp->enc_intr_limit = nvec;
-
/*
* Medford stores a single global copy of VPD, not per-PF as on
* Huntington.
/*
* Medford stores a single global copy of VPD, not per-PF as on
* Huntington.
rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail6:
- EFSYS_PROBE(fail6);
fail5:
EFSYS_PROBE(fail5);
fail4:
fail5:
EFSYS_PROBE(fail5);
fail4: