Add support to send PF FLR request to the management firmware to
bringup the device in clean slate. This cleanup is necessary
in some corner cases where the device would be left in a bad
state from its previous operations. The driver will send PF FLR
request before slowpath initialization.
Signed-off-by: Harish Patil <harish.patil@qlogic.com>
- SR-IOV PF
- Tunneling offloads
- SR-IOV PF
- Tunneling offloads
-- Reload of the PMD after a non-graceful termination
Supported QLogic Adapters
-------------------------
Supported QLogic Adapters
-------------------------
void OSAL_IOMEM *p_doorbells,
struct ecore_hw_prepare_params *p_params)
{
void OSAL_IOMEM *p_doorbells,
struct ecore_hw_prepare_params *p_params)
{
+ struct ecore_dev *p_dev = p_hwfn->p_dev;
enum _ecore_status_t rc = ECORE_SUCCESS;
/* Split PCI bars evenly between hwfns */
p_hwfn->regview = p_regview;
p_hwfn->doorbells = p_doorbells;
enum _ecore_status_t rc = ECORE_SUCCESS;
/* Split PCI bars evenly between hwfns */
p_hwfn->regview = p_regview;
p_hwfn->doorbells = p_doorbells;
- if (IS_VF(p_hwfn->p_dev))
return ecore_vf_hw_prepare(p_hwfn);
/* Validate that chip access is feasible */
return ecore_vf_hw_prepare(p_hwfn);
/* Validate that chip access is feasible */
/* First hwfn learns basic information, e.g., number of hwfns */
if (!p_hwfn->my_id) {
/* First hwfn learns basic information, e.g., number of hwfns */
if (!p_hwfn->my_id) {
- rc = ecore_get_dev_info(p_hwfn->p_dev);
+ rc = ecore_get_dev_info(p_dev);
if (rc != ECORE_SUCCESS)
goto err1;
}
if (rc != ECORE_SUCCESS)
goto err1;
}
+ if (p_hwfn == ECORE_LEADING_HWFN(p_dev) && !p_dev->recov_in_prog) {
+ rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
+ if (rc != ECORE_SUCCESS)
+ DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
+ }
+
/* Read the device configuration information from the HW and SHMEM */
rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
p_params->personality, p_params->drv_resc_alloc);
/* Read the device configuration information from the HW and SHMEM */
rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
p_params->personality, p_params->drv_resc_alloc);
goto err2;
}
#ifndef ASIC_ONLY
goto err2;
}
#ifndef ASIC_ONLY
- if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
+ if (CHIP_REV_IS_FPGA(p_dev)) {
DP_NOTICE(p_hwfn, false,
"FPGA: workaround; Prevent DMAE parities\n");
ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
DP_NOTICE(p_hwfn, false,
"FPGA: workaround; Prevent DMAE parities\n");
ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
return rc;
err2:
if (IS_LEAD_HWFN(p_hwfn))
return rc;
err2:
if (IS_LEAD_HWFN(p_hwfn))
- ecore_iov_free_hw_info(p_hwfn->p_dev);
+ ecore_iov_free_hw_info(p_dev);
ecore_mcp_free(p_hwfn);
err1:
ecore_hw_hwfn_free(p_hwfn);
ecore_mcp_free(p_hwfn);
err1:
ecore_hw_hwfn_free(p_hwfn);
+
+enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
+ struct ecore_ptt *p_ptt)
+{
+ u32 mcp_resp, mcp_param;
+
+ return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR,
+ 0, &mcp_resp, &mcp_param);
+}
struct resource_info *p_resc_info,
u32 *p_mcp_resp, u32 *p_mcp_param);
struct resource_info *p_resc_info,
u32 *p_mcp_resp, u32 *p_mcp_param);
+/**
+ * @brief - Initiates PF FLR
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ *
+ * @param return ECORE_SUCCESS upon success.
+ */
+enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
+ struct ecore_ptt *p_ptt);
+
#endif /* __ECORE_MCP_H__ */
#endif /* __ECORE_MCP_H__ */