net/enetc: improve prefetch in Rx ring clean

LS1028A does not have platform cache so any reads following a hardware
write will go directly to DDR.  Latency of such a read is in excess of
100 core cycles, so try to prefetch more in advance to mitigate this.
How much is worth prefetching really depends on traffic conditions.
With congested Rx this could go up to 4 cache lines or so.  But if
software keeps up with hardware and follows behind Rx PI by a cache line
then it's harmful in terms of performance to cache more.  We would only
prefetch data that's yet to be written by ENETC, which will be evicted
again anyway.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Gagandeep Singh <g.singh@nxp.com>