IBM Power architecture has different cache line size (128 bytes) than
x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to
override the default value 64 bytes to support IBM Power Architecture.
Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Acked-by: David Marchand <david.marchand@6wind.com>
size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2;
int align = 0;
#ifndef RTE_LIBRTE_MALLOC_DEBUG
size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2;
int align = 0;
#ifndef RTE_LIBRTE_MALLOC_DEBUG
- int overhead = 64 + 64;
+ int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE;
- int overhead = 64 + 64 + 64;
+ int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE + CACHE_LINE_SIZE;
#endif
rte_malloc_get_socket_stats(socket, &pre_stats);
#endif
rte_malloc_get_socket_stats(socket, &pre_stats);
#ifndef RTE_LIBRTE_MALLOC_DEBUG
int trailer_size = 0;
#else
#ifndef RTE_LIBRTE_MALLOC_DEBUG
int trailer_size = 0;
#else
+ int trailer_size = CACHE_LINE_SIZE;
- int overhead = 64 + trailer_size;
+ int overhead = CACHE_LINE_SIZE + trailer_size;
rte_malloc_get_socket_stats(socket, &pre_stats);
rte_malloc_get_socket_stats(socket, &pre_stats);
+CPU_CFLAGS ?= -m64 -DCACHE_LINE_SIZE=128
CPU_LDFLAGS ?=
CPU_ASFLAGS ?= -felf64
CPU_LDFLAGS ?=
CPU_ASFLAGS ?= -felf64