+#define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)