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0887aa7)
Updating a consumer index to HW doesn't require a memory barrier in case
that there's no updated data to be posted to HW, but a compiler barrier
is sufficient. rte_wmb() is replaced with rte_io_wmb() when it makes
changes visible to HW, not other core.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
return 0;
/* Update the consumer index. */
rxq->rq_ci = rq_ci >> sges_n;
return 0;
/* Update the consumer index. */
rxq->rq_ci = rq_ci >> sges_n;
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
#ifdef MLX5_PMD_SOFT_COUNTERS
/* Increment packets counter. */
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
#ifdef MLX5_PMD_SOFT_COUNTERS
/* Increment packets counter. */
txq->cq_ci = cq_ci;
txq->elts_tail = elts_tail;
/* Update the consumer index. */
txq->cq_ci = cq_ci;
txq->elts_tail = elts_tail;
/* Update the consumer index. */
+ rte_compiler_barrier();
*txq->cq_db = rte_cpu_to_be_32(cq_ci);
}
*txq->cq_db = rte_cpu_to_be_32(cq_ci);
}
wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
RTE_PKTMBUF_HEADROOM);
rxq->rq_ci += n;
wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
RTE_PKTMBUF_HEADROOM);
rxq->rq_ci += n;
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
}
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
}
+ rte_compiler_barrier();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
return rcvd_pkt;
}
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
return rcvd_pkt;
}