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9058afa)
Currently otx2_mbox_get_rsp_xxx get response once AF driver
interrupts after completion. But this function will get into
deadlock if called in another interrupt context.
To avoid it, implemented another version of this function which polls
on dedicated memory for a given timeout.
Also after clearing interrupt, there could UP messages available for
processing. So irq handler must check mbox messages.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
+CFLAGS += -DALLOW_EXPERIMENTAL_API
ifneq ($(CONFIG_RTE_ARCH_64),y)
CFLAGS += -Wno-int-to-pointer-cast
ifneq ($(CONFIG_RTE_ARCH_64),y)
CFLAGS += -Wno-int-to-pointer-cast
# Copyright(C) 2019 Marvell International Ltd.
#
# Copyright(C) 2019 Marvell International Ltd.
#
+allow_experimental_apis = true
+
sources= files('otx2_dev.c',
'otx2_irq.c',
'otx2_mbox.c',
sources= files('otx2_dev.c',
'otx2_irq.c',
'otx2_mbox.c',
intr = otx2_read64(dev->bar2 + RVU_VF_INT);
if (intr == 0)
intr = otx2_read64(dev->bar2 + RVU_VF_INT);
if (intr == 0)
+ otx2_base_dbg("Proceeding to check mbox UP messages if any");
otx2_write64(intr, dev->bar2 + RVU_VF_INT);
otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
otx2_write64(intr, dev->bar2 + RVU_VF_INT);
otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
- if (intr) {
- /* First process all configuration messages */
- otx2_process_msgs(dev, dev->mbox);
- /* Process Uplink messages */
- otx2_process_msgs_up(dev, &dev->mbox_up);
- }
+ /* First process all configuration messages */
+ otx2_process_msgs(dev, dev->mbox);
+
+ /* Process Uplink messages */
+ otx2_process_msgs_up(dev, &dev->mbox_up);
intr = otx2_read64(dev->bar2 + RVU_PF_INT);
if (intr == 0)
intr = otx2_read64(dev->bar2 + RVU_PF_INT);
if (intr == 0)
+ otx2_base_dbg("Proceeding to check mbox UP messages if any");
otx2_write64(intr, dev->bar2 + RVU_PF_INT);
otx2_write64(intr, dev->bar2 + RVU_PF_INT);
otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
- if (intr) {
- /* First process all configuration messages */
- otx2_process_msgs(dev, dev->mbox);
- /* Process Uplink messages */
- otx2_process_msgs_up(dev, &dev->mbox_up);
- }
+ /* First process all configuration messages */
+ otx2_process_msgs(dev, dev->mbox);
+
+ /* Process Uplink messages */
+ otx2_process_msgs_up(dev, &dev->mbox_up);
{
int up_direction = MBOX_DIR_PFAF_UP;
int rc, direction = MBOX_DIR_PFAF;
{
int up_direction = MBOX_DIR_PFAF_UP;
int rc, direction = MBOX_DIR_PFAF;
+ uint64_t intr_offset = RVU_PF_INT;
struct otx2_dev *dev = otx2_dev;
uintptr_t bar2, bar4;
uint64_t bar4_addr;
struct otx2_dev *dev = otx2_dev;
uintptr_t bar2, bar4;
uint64_t bar4_addr;
if (otx2_dev_is_vf(dev)) {
direction = MBOX_DIR_VFPF;
up_direction = MBOX_DIR_VFPF_UP;
if (otx2_dev_is_vf(dev)) {
direction = MBOX_DIR_VFPF;
up_direction = MBOX_DIR_VFPF_UP;
+ intr_offset = RVU_VF_INT;
}
/* Initialize the local mbox */
}
/* Initialize the local mbox */
- rc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1);
+ rc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1,
+ intr_offset);
if (rc)
goto error;
dev->mbox = &dev->mbox_local;
if (rc)
goto error;
dev->mbox = &dev->mbox_local;
- rc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1);
+ rc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1,
+ intr_offset);
}
/* Init mbox object */
rc = otx2_mbox_init(&dev->mbox_vfpf, (uintptr_t)hwbase,
}
/* Init mbox object */
rc = otx2_mbox_init(&dev->mbox_vfpf, (uintptr_t)hwbase,
- bar2, MBOX_DIR_PFVF, pci_dev->max_vfs);
+ bar2, MBOX_DIR_PFVF, pci_dev->max_vfs,
+ intr_offset);
if (rc)
goto iounmap;
/* PF -> VF UP messages */
rc = otx2_mbox_init(&dev->mbox_vfpf_up, (uintptr_t)hwbase,
if (rc)
goto iounmap;
/* PF -> VF UP messages */
rc = otx2_mbox_init(&dev->mbox_vfpf_up, (uintptr_t)hwbase,
- bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs);
+ bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs,
+ intr_offset);
if (rc)
goto mbox_fini;
}
if (rc)
goto mbox_fini;
}
#include <rte_cycles.h>
#include "otx2_mbox.h"
#include <rte_cycles.h>
#include "otx2_mbox.h"
#define RVU_AF_AFPF_MBOX0 (0x02000)
#define RVU_AF_AFPF_MBOX1 (0x02008)
#define RVU_AF_AFPF_MBOX0 (0x02000)
#define RVU_AF_AFPF_MBOX1 (0x02008)
-otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,
- uintptr_t reg_base, int direction, int ndevs)
+otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
+ int direction, int ndevs, uint64_t intr_offset)
{
struct otx2_mbox_dev *mdev;
int devid;
{
struct otx2_mbox_dev *mdev;
int devid;
+ mbox->intr_offset = intr_offset;
mbox->reg_base = reg_base;
mbox->hwbase = hwbase;
mbox->reg_base = reg_base;
mbox->hwbase = hwbase;
+/**
+ * Polling for given wait time to get mailbox response
+ */
+static int
+mbox_poll(struct otx2_mbox *mbox, uint32_t wait)
+{
+ uint32_t timeout = 0, sleep = 1;
+ uint32_t wait_us = wait * 1000;
+ uint64_t rsp_reg = 0;
+ uintptr_t reg_addr;
+
+ reg_addr = mbox->reg_base + mbox->intr_offset;
+ do {
+ rsp_reg = otx2_read64(reg_addr);
+
+ if (timeout >= wait_us)
+ return -ETIMEDOUT;
+
+ rte_delay_us(sleep);
+ timeout += sleep;
+ } while (!rsp_reg);
+
+ rte_smp_rmb();
+
+ /* Clear interrupt */
+ otx2_write64(rsp_reg, reg_addr);
+
+ /* Reset mbox */
+ otx2_mbox_reset(mbox, 0);
+
+ return 0;
+}
+
/**
* @internal
* Wait and get mailbox response with timeout
/**
* @internal
* Wait and get mailbox response with timeout
- rc = mbox_wait(mbox, devid, tmo);
- if (rc)
- return rc;
+ if (rte_thread_is_intr())
+ rc = mbox_poll(mbox, tmo);
+ else
+ rc = mbox_wait(mbox, devid, tmo);
+
+ if (!rc)
+ rc = mdev->num_msgs;
- return mdev->msgs_acked;
uint16_t tx_size; /* Size of Tx region */
uint16_t ndevs; /* The number of peers */
struct otx2_mbox_dev *dev;
uint16_t tx_size; /* Size of Tx region */
uint16_t ndevs; /* The number of peers */
struct otx2_mbox_dev *dev;
+ uint64_t intr_offset; /* Offset to interrupt register */
};
/* Header which precedes all mbox messages */
};
/* Header which precedes all mbox messages */
const char *otx2_mbox_id2name(uint16_t id);
int otx2_mbox_id2size(uint16_t id);
void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
const char *otx2_mbox_id2name(uint16_t id);
int otx2_mbox_id2size(uint16_t id);
void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
-int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,
- uintptr_t reg_base, int direction, int ndevs);
+int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
+ int direction, int ndevsi, uint64_t intr_offset);
void otx2_mbox_fini(struct otx2_mbox *mbox);
void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
void otx2_mbox_fini(struct otx2_mbox *mbox);
void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);