Support added for physical addressing mode and
change driver flags to don't care.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
* Added support for VXLAN-GPE packet.
* Added support for VXLAN-GPE classification.
* Added support for VXLAN-GPE packet.
* Added support for VXLAN-GPE classification.
+* **Updated the ENETC driver.**
+
+ New features:
+
+ * Added physical addressing mode support
+
* **Updated the QuickAssist Technology PMD.**
Added support for AES-XTS with 128 and 256 bit AES keys.
* **Updated the QuickAssist Technology PMD.**
Added support for AES-XTS with 128 and 256 bit AES keys.
/* SPDX-License-Identifier: BSD-3-Clause
/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2018-2019 NXP
enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
{
int idx = tx_ring->index;
enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
{
int idx = tx_ring->index;
+ phys_addr_t bd_address;
- base_addr = (uintptr_t)tx_ring->bd_base;
+ bd_address = (phys_addr_t)
+ rte_mem_virt2iova((const void *)tx_ring->bd_base);
enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
- lower_32_bits((uint64_t)base_addr));
+ lower_32_bits((uint64_t)bd_address));
enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
- upper_32_bits((uint64_t)base_addr));
+ upper_32_bits((uint64_t)bd_address));
enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
ENETC_RTBLENR_LEN(tx_ring->bd_count));
enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
ENETC_RTBLENR_LEN(tx_ring->bd_count));
struct rte_mempool *mb_pool)
{
int idx = rx_ring->index;
struct rte_mempool *mb_pool)
{
int idx = rx_ring->index;
+ phys_addr_t bd_address;
- base_addr = (uintptr_t)rx_ring->bd_base;
+ bd_address = (phys_addr_t)
+ rte_mem_virt2iova((const void *)rx_ring->bd_base);
enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
- lower_32_bits((uint64_t)base_addr));
+ lower_32_bits((uint64_t)bd_address));
enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
- upper_32_bits((uint64_t)base_addr));
+ upper_32_bits((uint64_t)bd_address));
enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
ENETC_RTBLENR_LEN(rx_ring->bd_count));
enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
ENETC_RTBLENR_LEN(rx_ring->bd_count));
static struct rte_pci_driver rte_enetc_pmd = {
.id_table = pci_id_enetc_map,
static struct rte_pci_driver rte_enetc_pmd = {
.id_table = pci_id_enetc_map,
- .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
.probe = enetc_pci_probe,
.remove = enetc_pci_remove,
};
.probe = enetc_pci_probe,
.remove = enetc_pci_remove,
};
/* SPDX-License-Identifier: BSD-3-Clause
/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2018-2019 NXP
txbd->buf_len = txbd->frm_len;
txbd->flags = rte_cpu_to_le_16(ENETC_TXBD_FLAGS_F);
txbd->addr = (uint64_t)(uintptr_t)
txbd->buf_len = txbd->frm_len;
txbd->flags = rte_cpu_to_le_16(ENETC_TXBD_FLAGS_F);
txbd->addr = (uint64_t)(uintptr_t)
- rte_cpu_to_le_64((size_t)tx_swbd->buffer_addr->buf_addr +
+ rte_cpu_to_le_64((size_t)tx_swbd->buffer_addr->buf_iova +
tx_swbd->buffer_addr->data_off);
i++;
start++;
tx_swbd->buffer_addr->data_off);
i++;
start++;
rx_swbd->buffer_addr =
rte_cpu_to_le_64(rte_mbuf_raw_alloc(rx_ring->mb_pool));
rxbd->w.addr = (uint64_t)(uintptr_t)
rx_swbd->buffer_addr =
rte_cpu_to_le_64(rte_mbuf_raw_alloc(rx_ring->mb_pool));
rxbd->w.addr = (uint64_t)(uintptr_t)
- rx_swbd->buffer_addr->buf_addr +
+ rx_swbd->buffer_addr->buf_iova +
rx_swbd->buffer_addr->data_off;
/* clear 'R" as well */
rxbd->r.lstatus = 0;
rx_swbd->buffer_addr->data_off;
/* clear 'R" as well */
rxbd->r.lstatus = 0;