+
+static void __attribute__((cold))
+fm10k_tx_queue_release_mbufs_vec(struct fm10k_tx_queue *txq)
+{
+ unsigned i;
+ const uint16_t max_desc = (uint16_t)(txq->nb_desc - 1);
+
+ if (txq->sw_ring == NULL || txq->nb_free == max_desc)
+ return;
+
+ /* release the used mbufs in sw_ring */
+ for (i = txq->next_dd - (txq->rs_thresh - 1);
+ i != txq->next_free;
+ i = (i + 1) & max_desc)
+ rte_pktmbuf_free_seg(txq->sw_ring[i]);
+
+ txq->nb_free = max_desc;
+
+ /* reset tx_entry */
+ for (i = 0; i < txq->nb_desc; i++)
+ txq->sw_ring[i] = NULL;
+
+ rte_free(txq->sw_ring);
+ txq->sw_ring = NULL;
+}
+
+static void __attribute__((cold))
+fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
+{
+ static const struct fm10k_tx_desc zeroed_desc = {0};
+ struct rte_mbuf **txe = txq->sw_ring;
+ uint16_t i;
+
+ /* Zero out HW ring memory */
+ for (i = 0; i < txq->nb_desc; i++)
+ txq->hw_ring[i] = zeroed_desc;
+
+ /* Initialize SW ring entries */
+ for (i = 0; i < txq->nb_desc; i++)
+ txe[i] = NULL;
+
+ txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
+ txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
+
+ txq->next_free = 0;
+ txq->nb_used = 0;
+ /* Always allow 1 descriptor to be un-allocated to avoid
+ * a H/W race condition
+ */
+ txq->nb_free = (uint16_t)(txq->nb_desc - 1);
+ FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);
+}