The meson build never checked for the presence of rdrand and rdseed
instructions, while make build never checked for rdseed. Ensure builds
always have the appropriate checks - and therefore defines - for these
instructions. For runtime, we also add in rdseed to the list of known
bits returned from cpuid() instruction, so we can confirm its presence at
application init time.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Tested-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
endforeach
optional_flags = ['AES', 'PCLMUL',
endforeach
optional_flags = ['AES', 'PCLMUL',
- 'AVX', 'AVX2', 'AVX512F']
+ 'AVX', 'AVX2', 'AVX512F',
+ 'RDRND', 'RDSEED']
foreach f:optional_flags
if cc.get_define('__@0@__'.format(f), args: machine_args) == '1'
if f == 'PCLMUL' # special case flags with different defines
f = 'PCLMULQDQ'
foreach f:optional_flags
if cc.get_define('__@0@__'.format(f), args: machine_args) == '1'
if f == 'PCLMUL' # special case flags with different defines
f = 'PCLMULQDQ'
+ elif f == 'RDRND'
+ f = 'RDRAND'
endif
dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1)
compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
endif
dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1)
compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)
FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)
+ FEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18)
FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)
FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)
FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)
FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)
RTE_CPUFLAG_INVPCID, /**< INVPCID */
RTE_CPUFLAG_RTM, /**< Transactional memory */
RTE_CPUFLAG_AVX512F, /**< AVX512F */
RTE_CPUFLAG_INVPCID, /**< INVPCID */
RTE_CPUFLAG_RTM, /**< Transactional memory */
RTE_CPUFLAG_AVX512F, /**< AVX512F */
+ RTE_CPUFLAG_RDSEED, /**< RDSEED instruction */
/* (EAX 80000001h) ECX features */
RTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */
/* (EAX 80000001h) ECX features */
RTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */
+ifneq ($(filter $(AUTO_CPUFLAGS),__RDSEED__),)
+CPUFLAGS += RDSEED
+endif
+
ifneq ($(filter $(AUTO_CPUFLAGS),__FSGSBASE__),)
CPUFLAGS += FSGSBASE
endif
ifneq ($(filter $(AUTO_CPUFLAGS),__FSGSBASE__),)
CPUFLAGS += FSGSBASE
endif