common/cnxk: add BPHY CGX/RPM initialization and cleanup
authorTomasz Duszynski <tduszynski@marvell.com>
Mon, 21 Jun 2021 15:04:18 +0000 (17:04 +0200)
committerThomas Monjalon <thomas@monjalon.net>
Mon, 5 Jul 2021 21:06:44 +0000 (23:06 +0200)
Add support for low level initialization and cleanup of baseband
PHY CGX/RPM blocks.

Initialization and cleanup are related hence are in the same patch.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
drivers/common/cnxk/meson.build
drivers/common/cnxk/roc_api.h
drivers/common/cnxk/roc_bphy_cgx.c [new file with mode: 0644]
drivers/common/cnxk/roc_bphy_cgx.h [new file with mode: 0644]
drivers/common/cnxk/version.map

index 178bce7..59975fd 100644 (file)
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_bphy_cgx.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
index 67f5d13..256d8c6 100644 (file)
 /* Idev */
 #include "roc_idev.h"
 
+/* Baseband phy cgx */
+#include "roc_bphy_cgx.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
new file mode 100644 (file)
index 0000000..029d410
--- /dev/null
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+/*
+ * CN10K stores number of lmacs in 4 bit filed
+ * in contraty to CN9K which uses only 3 bits.
+ *
+ * In theory masks should differ yet on CN9K
+ * bits beyond specified range contain zeros.
+ *
+ * Hence common longer mask may be used.
+ */
+#define CGX_CMRX_RX_LMACS      0x128
+#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+
+static uint64_t
+roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
+{
+       int shift = roc_model_is_cn10k() ? 20 : 18;
+       uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+       return plt_read64(base + (lmac << shift) + offset);
+}
+
+static unsigned int
+roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
+{
+       uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
+                                                GENMASK_ULL(25, 24);
+
+       return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
+}
+
+int
+roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
+{
+       uint64_t val;
+
+       if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
+               return -EINVAL;
+
+       val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
+       val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
+       if (roc_model_is_cn9k())
+               val = GENMASK_ULL(val - 1, 0);
+       roc_cgx->lmac_bmap = val;
+       roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
+
+       return 0;
+}
+
+int
+roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
+{
+       if (!roc_cgx)
+               return -EINVAL;
+
+       return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
new file mode 100644 (file)
index 0000000..aac2c26
--- /dev/null
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_H_
+#define _ROC_BPHY_CGX_H_
+
+#include "roc_api.h"
+
+struct roc_bphy_cgx {
+       uint64_t bar0_pa;
+       void *bar0_va;
+       uint64_t lmac_bmap;
+       unsigned int id;
+} __plt_cache_aligned;
+
+__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+
+#endif /* _ROC_BPHY_CGX_H_ */
index 8e67c83..1db4d10 100644 (file)
@@ -9,6 +9,8 @@ INTERNAL {
        cnxk_logtype_sso;
        cnxk_logtype_tim;
        cnxk_logtype_tm;
+       roc_bphy_cgx_dev_fini;
+       roc_bphy_cgx_dev_init;
        roc_clk_freq_get;
        roc_error_msg_get;
        roc_idev_lmt_base_addr_get;