plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
lf->fc_addr = (uint64_t *)addr;
+ lf->fc_hyst_bits = plt_log2_u32(lf->nb_desc) / 2;
+ lf->fc_thresh = lf->nb_desc - (lf->nb_desc % (1 << lf->fc_hyst_bits));
}
int
lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);
lf_ctl.s.ena = 1;
lf_ctl.s.fc_ena = 1;
- lf_ctl.s.fc_up_crossing = 1;
- lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS;
+ lf_ctl.s.fc_up_crossing = 0;
+ lf_ctl.s.fc_hyst_bits = lf->fc_hyst_bits;
plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
cpt_lf_dump(lf);
uint16_t msixoff;
uint16_t pf_func;
uint64_t *fc_addr;
+ uint32_t fc_hyst_bits;
+ uint64_t fc_thresh;
uint64_t io_addr;
uint8_t *iq_vaddr;
struct roc_nix *inl_outb_nix;
uint16_t zombie_thres;
};
+static inline int
+roc_cpt_is_iq_full(struct roc_cpt_lf *lf)
+{
+ if (*lf->fc_addr < lf->fc_thresh)
+ return 0;
+
+ return 1;
+}
+
int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
struct roc_cpt_rxc_time_cfg *cfg);
int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
#ifndef _ROC_CPT_PRIV_H_
#define _ROC_CPT_PRIV_H_
-/* Set number of hystbits to 6.
- * This will trigger the FC writes whenever number of outstanding commands in
- * the queue becomes multiple of 32.
- */
-#define CPT_FC_NUM_HYST_BITS 6
-
struct cpt {
struct plt_pci_device *pci_dev;
struct dev dev;