net/sfc/base: move datapath config to ef10 NIC board cfg

Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>

diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index 4a50955..e1708ab 100644 (file)
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -1161,10 +1161,6 @@ efx_mcdi_get_vector_cfg(
        __out_opt       uint32_t *pf_nvecp,
        __out_opt       uint32_t *vf_nvecp);
 
-extern __checkReturn   efx_rc_t
-ef10_get_datapath_caps(
-       __in            efx_nic_t *enp);
-
 extern __checkReturn   efx_rc_t
 ef10_get_vi_window_shift(
        __in            efx_nic_t *enp,

diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 8e9d7a1..e7fa7b8 100644 (file)
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -989,7 +989,7 @@ fail1:
        return (rc);
 }
 
-       __checkReturn   efx_rc_t
+static __checkReturn   efx_rc_t
 ef10_get_datapath_caps(
        __in            efx_nic_t *enp)
 {
@@ -1631,13 +1631,19 @@ ef10_nic_board_cfg(
        epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
        epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
+       /* Check capabilities of running datapath firmware */
+       if ((rc = ef10_get_datapath_caps(enp)) != 0)
+               goto fail8;
+
        /* Get remaining controller-specific board config */
        if ((rc = enop->eno_board_cfg(enp)) != 0)
                if (rc != EACCES)
-                       goto fail8;
+                       goto fail9;
 
        return (0);
 
+fail9:
+       EFSYS_PROBE(fail9);
 fail8:
        EFSYS_PROBE(fail8);
 fail7:

diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index d33d2db..95b48a7 100644 (file)
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -201,10 +201,6 @@ hunt_board_cfg(
 
        encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
 
-       /* Check capabilities of running datapath firmware */
-       if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail5;
-
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
        encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
@@ -253,13 +249,13 @@ hunt_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail6;
+               goto fail5;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail7;
+                       goto fail6;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -275,7 +271,7 @@ hunt_board_cfg(
        encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
        if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-               goto fail8;
+               goto fail7;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
        /* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -283,8 +279,6 @@ hunt_board_cfg(
 
        return (0);
 
-fail8:
-       EFSYS_PROBE(fail8);
 fail7:
        EFSYS_PROBE(fail7);
 fail6:

diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index afaafb9..f383b31 100644 (file)
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -124,17 +124,13 @@ medford2_board_cfg(
        encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
                    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
-       /* Check capabilities of running datapath firmware */
-       if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail4;
-
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
 
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail5;
+                       goto fail4;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -186,13 +182,13 @@ medford2_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail6;
+               goto fail5;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail7;
+                       goto fail6;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -215,14 +211,12 @@ medford2_board_cfg(
 
        rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail8;
+               goto fail7;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail8:
-       EFSYS_PROBE(fail8);
 fail7:
        EFSYS_PROBE(fail7);
 fail6:

diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index afa6493..5e9d391 100644 (file)
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -123,17 +123,13 @@ medford_board_cfg(
        encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
                    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
-       /* Check capabilities of running datapath firmware */
-       if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail3;
-
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
 
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail4;
+                       goto fail3;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -185,13 +181,13 @@ medford_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail5;
+               goto fail4;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail6;
+                       goto fail5;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -214,14 +210,12 @@ medford_board_cfg(
 
        rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail7;
+               goto fail6;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail7:
-       EFSYS_PROBE(fail7);
 fail6:
        EFSYS_PROBE(fail6);
 fail5: