]> git.droids-corp.org - dpdk.git/commitdiff
net/ngbe: fix PCIe related operations with bus API
authorJiawen Wu <jiawenwu@trustnetic.com>
Mon, 30 May 2022 09:30:13 +0000 (17:30 +0800)
committerFerruh Yigit <ferruh.yigit@xilinx.com>
Tue, 31 May 2022 07:42:16 +0000 (09:42 +0200)
When using mailbox to request firmware to enable or disable PCIe bus
master, there is a small probability that mailbox cannot respond.
Change to use rte_pci_read_config() and rte_pci_write_config(), to
avoid this problem.

Fixes: ac6c5e9af56a ("net/ngbe: fix Tx hang on queue disable")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
drivers/net/ngbe/base/ngbe_hw.c
drivers/net/ngbe/base/ngbe_osdep.h
drivers/net/ngbe/ngbe_ethdev.c

index 050649e0a645b46d808bd108cf45d9ec64c4f7bf..facc1d9e82922d386bf6f22fb9fc20675bc042f6 100644 (file)
@@ -1058,17 +1058,30 @@ out:
  **/
 s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
 {
+       struct rte_pci_device *pci_dev = (struct rte_pci_device *)hw->back;
        s32 status = 0;
-       u16 addr = 0x04;
-       u32 data, i;
+       s32 ret = 0;
+       u32 i;
+       u16 reg;
+
+       ret = rte_pci_read_config(pci_dev, &reg,
+                       sizeof(reg), PCI_COMMAND);
+       if (ret != sizeof(reg)) {
+               DEBUGOUT("Cannot read command from PCI config space!\n");
+               return -1;
+       }
 
-       ngbe_hic_pcie_read(hw, addr, &data, 4);
        if (enable)
-               data |= 0x04;
+               reg |= PCI_COMMAND_MASTER;
        else
-               data &= ~0x04;
+               reg &= ~PCI_COMMAND_MASTER;
 
-       ngbe_hic_pcie_write(hw, addr, &data, 4);
+       ret = rte_pci_write_config(pci_dev, &reg,
+                       sizeof(reg), PCI_COMMAND);
+       if (ret != sizeof(reg)) {
+               DEBUGOUT("Cannot write command to PCI config space!\n");
+               return -1;
+       }
 
        if (enable)
                goto out;
index b62d793191ff1b0d24ce262c67a9e451b06d9919..bf1fa30312cbb2cb0c2fa9fd676c03644fc34928 100644 (file)
@@ -19,6 +19,7 @@
 #include <rte_config.h>
 #include <rte_io.h>
 #include <rte_ether.h>
+#include <rte_bus_pci.h>
 
 #include "../ngbe_logs.h"
 
@@ -180,4 +181,7 @@ static inline u64 REVERT_BIT_MASK64(u64 mask)
 #define ETH_P_8021Q      0x8100
 #define ETH_P_8021AD     0x88A8
 
+#define PCI_COMMAND            0x04
+#define  PCI_COMMAND_MASTER    0x4
+
 #endif /* _NGBE_OS_H_ */
index 9df9f824a11680ab0aa7c850e5276c58f98f3d44..5ac1c27a587760bab7075a3f8876a7510a7850af 100644 (file)
@@ -356,6 +356,7 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
        eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 
        /* Vendor and Device ID need to be set before init of shared code */
+       hw->back = pci_dev;
        hw->device_id = pci_dev->id.device_id;
        hw->vendor_id = pci_dev->id.vendor_id;
        hw->sub_system_id = pci_dev->id.subsystem_device_id;