**/
s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
{
+ struct rte_pci_device *pci_dev = (struct rte_pci_device *)hw->back;
s32 status = 0;
- u16 addr = 0x04;
- u32 data, i;
+ s32 ret = 0;
+ u32 i;
+ u16 reg;
+
+ ret = rte_pci_read_config(pci_dev, ®,
+ sizeof(reg), PCI_COMMAND);
+ if (ret != sizeof(reg)) {
+ DEBUGOUT("Cannot read command from PCI config space!\n");
+ return -1;
+ }
- ngbe_hic_pcie_read(hw, addr, &data, 4);
if (enable)
- data |= 0x04;
+ reg |= PCI_COMMAND_MASTER;
else
- data &= ~0x04;
+ reg &= ~PCI_COMMAND_MASTER;
- ngbe_hic_pcie_write(hw, addr, &data, 4);
+ ret = rte_pci_write_config(pci_dev, ®,
+ sizeof(reg), PCI_COMMAND);
+ if (ret != sizeof(reg)) {
+ DEBUGOUT("Cannot write command to PCI config space!\n");
+ return -1;
+ }
if (enable)
goto out;
#include <rte_config.h>
#include <rte_io.h>
#include <rte_ether.h>
+#include <rte_bus_pci.h>
#include "../ngbe_logs.h"
#define ETH_P_8021Q 0x8100
#define ETH_P_8021AD 0x88A8
+#define PCI_COMMAND 0x04
+#define PCI_COMMAND_MASTER 0x4
+
#endif /* _NGBE_OS_H_ */
eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
/* Vendor and Device ID need to be set before init of shared code */
+ hw->back = pci_dev;
hw->device_id = pci_dev->id.device_id;
hw->vendor_id = pci_dev->id.vendor_id;
hw->sub_system_id = pci_dev->id.subsystem_device_id;