]> git.droids-corp.org - dpdk.git/commitdiff
net/sfc/base: remove min/max defines for number of events
authorIgor Romanov <igor.romanov@oktetlabs.ru>
Thu, 7 Feb 2019 16:29:13 +0000 (16:29 +0000)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 8 Feb 2019 10:35:41 +0000 (11:35 +0100)
EF100/Riverhead has different min/max limits. So, these limits should
be a part of NIC config, not defines common for all NIC families.

Signed-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
drivers/net/sfc/base/ef10_ev.c
drivers/net/sfc/base/ef10_impl.h
drivers/net/sfc/base/efx.h
drivers/net/sfc/base/efx_ev.c
drivers/net/sfc/base/hunt_nic.c
drivers/net/sfc/base/medford2_nic.c
drivers/net/sfc/base/medford_nic.c
drivers/net/sfc/base/siena_impl.h
drivers/net/sfc/base/siena_nic.c

index cdf835f03609008b9377eb914ad9895890c2146d..12125c6db047fdc38aa61b0040be771eaca0bd03 100644 (file)
@@ -123,7 +123,7 @@ efx_mcdi_init_evq(
 {
        efx_mcdi_req_t req;
        EFX_MCDI_DECLARE_BUF(payload,
-               MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
+               MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EF10_EVQ_MAXNEVS)),
                MC_CMD_INIT_EVQ_OUT_LEN);
        efx_qword_t *dma_addr;
        uint64_t addr;
@@ -259,7 +259,7 @@ efx_mcdi_init_evq_v2(
 {
        efx_mcdi_req_t req;
        EFX_MCDI_DECLARE_BUF(payload,
-               MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
+               MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EF10_EVQ_MAXNEVS)),
                MC_CMD_INIT_EVQ_V2_OUT_LEN);
        boolean_t interrupting;
        unsigned int evq_type;
@@ -446,11 +446,12 @@ ef10_ev_qcreate(
        efx_rc_t rc;
 
        _NOTE(ARGUNUSED(id))    /* buftbl id managed by MC */
-       EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
-       EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
+       EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
+       EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
 
        if (!ISP2(ndescs) ||
-           (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
+           (ndescs < encp->enc_evq_min_nevs) ||
+           (ndescs > encp->enc_evq_max_nevs)) {
                rc = EINVAL;
                goto fail1;
        }
@@ -563,9 +564,9 @@ ef10_ev_qprime(
        rptr = count & eep->ee_mask;
 
        if (enp->en_nic_cfg.enc_bug35388_workaround) {
-               EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
+               EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
                    (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
-               EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
+               EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
                    (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
 
                EFX_POPULATE_DWORD_2(dword,
index bf71b5a18fe1cee066814f4d110c9ccb220ce353..44f7f635d585709ff27d10eefd80d0cf19cb952d 100644 (file)
@@ -11,6 +11,9 @@
 extern "C" {
 #endif
 
+#define        EF10_EVQ_MAXNEVS        32768
+#define        EF10_EVQ_MINNEVS        512
+
 #define        EF10_RXQ_MAXNDESCS      4096
 #define        EF10_RXQ_MINNDESCS      512
 
index 06ce3d2fc760afd0a8ef1b05344d5fcc3c299be6..80a6419e385dc337d102c0e3a12e54e1a3932699 100644 (file)
@@ -1271,6 +1271,8 @@ typedef struct efx_nic_cfg_s {
        uint32_t                enc_evq_limit;
        uint32_t                enc_txq_limit;
        uint32_t                enc_rxq_limit;
+       uint32_t                enc_evq_max_nevs;
+       uint32_t                enc_evq_min_nevs;
        uint32_t                enc_rxq_max_ndescs;
        uint32_t                enc_rxq_min_ndescs;
        uint32_t                enc_txq_max_ndescs;
@@ -1976,6 +1978,10 @@ extern           void
 efx_ev_fini(
        __in            efx_nic_t *enp);
 
+/*
+ * These symbols are deprecated and will be removed.
+ * Use the fields from efx_nic_cfg_t instead.
+ */
 #define        EFX_EVQ_MAXNEVS         32768
 #define        EFX_EVQ_MINNEVS         512
 
index 907c4249fc656e76000e83a840973cd921854b5d..f1788cad25718dd5dd355161ec52ee311afd029d 100644 (file)
@@ -1285,11 +1285,12 @@ siena_ev_qcreate(
 
        _NOTE(ARGUNUSED(esmp))
 
-       EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
-       EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
+       EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
+       EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
 
        if (!ISP2(ndescs) ||
-           (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
+           (ndescs < encp->enc_evq_min_nevs) ||
+           (ndescs > encp->enc_evq_max_nevs)) {
                rc = EINVAL;
                goto fail1;
        }
@@ -1304,9 +1305,10 @@ siena_ev_qcreate(
                goto fail3;
        }
 #endif
-       for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
+       for (size = 0;
+           (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
            size++)
-               if ((1 << size) == (int)(ndescs / EFX_EVQ_MINNEVS))
+               if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
                        break;
        if (id + (1 << size) >= encp->enc_buftbl_limit) {
                rc = EINVAL;
index ae8a0085e906e5710f3855e6cad8a859cd609af4..755a377f0d8e835d0a1649ff73fee738b06d3b7c 100644 (file)
@@ -190,6 +190,9 @@ hunt_board_cfg(
        encp->enc_rx_buf_align_start = 1;
        encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
 
+       encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
+       encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
+
        encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
        encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
 
index 87c97b5db65a2b45c51dbc873665602d595483e5..3274744d9c535db165ee739964316f021461ec7d 100644 (file)
@@ -114,6 +114,9 @@ medford2_board_cfg(
        }
        encp->enc_rx_buf_align_end = end_padding;
 
+       encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
+       encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
+
        encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
        encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
 
index c5d91974294234848d9e1a488dc84ca398bb467d..cb107fe75a6055e51a3cf30e979764929ddc7d6e 100644 (file)
@@ -112,6 +112,9 @@ medford_board_cfg(
        }
        encp->enc_rx_buf_align_end = end_padding;
 
+       encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
+       encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
+
        encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
        encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
 
index 90f71d9c4664d172d34c3311dab1e7cee81c6463..675e49953694e0f1db652dd9b514df1688c185ee 100644 (file)
@@ -24,6 +24,9 @@ extern "C" {
 #endif
 #define        EFX_TXQ_DC_NDESCS(_dcsize)      (8 << (_dcsize))
 
+#define        SIENA_EVQ_MAXNEVS       32768
+#define        SIENA_EVQ_MINNEVS       512
+
 #define        SIENA_TXQ_MAXNDESCS     4096
 #define        SIENA_TXQ_MINNDESCS     512
 
index 341abd8f6ad0a659a707219825b6682f7d2a6eed..4962a65c573ce4cbfe68c165e749e49b8b8994b6 100644 (file)
@@ -149,6 +149,9 @@ siena_board_cfg(
        encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
        encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
 
+       encp->enc_evq_max_nevs = SIENA_EVQ_MAXNEVS;
+       encp->enc_evq_min_nevs = SIENA_EVQ_MINNEVS;
+
        encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
        encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;