examples/ipsec-secgw: fix SPI byte order in flow item

SPI field is defined in the RFC2406 [1] as a big endian field it should be
provided in its final form to the drivers through RTE flow.

[1] https://tools.ietf.org/html/rfc2406

Fixes: ec17993a145a ("examples/ipsec-secgw: support security offload")
Cc: stable@dpdk.org
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>

diff --git a/examples/ipsec-secgw/ipsec.c b/examples/ipsec-secgw/ipsec.c
index 4ef446d..a478b6e 100644 (file)
--- a/examples/ipsec-secgw/ipsec.c
+++ b/examples/ipsec-secgw/ipsec.c
@@ -166,7 +166,7 @@ create_session(struct ipsec_ctx *ipsec_ctx, struct ipsec_sa *sa)
                        sa->pattern[2].type = RTE_FLOW_ITEM_TYPE_ESP;
                        sa->pattern[2].spec = &sa->esp_spec;
                        sa->pattern[2].mask = &rte_flow_item_esp_mask;
-                       sa->esp_spec.hdr.spi = sa->spi;
+                       sa->esp_spec.hdr.spi = rte_cpu_to_be_32(sa->spi);
 
                        sa->pattern[3].type = RTE_FLOW_ITEM_TYPE_END;