u8 support_intr:1;
/* MSI-X vector table entry number */
u16 intr_vector_num:12;
- u64 rsvd:51; /* Reserved */
+ u64 rsvd:50; /* Reserved */
+ u64 seu_support:1;
};
};
};
struct feature_fme_ras_catfaterror ras_catfaterr;
struct feature_fme_ras_error_inj ras_error_inj;
struct feature_fme_error_capability fme_err_capability;
+ u64 seu_emr_l;
+ u64 seu_emr_h;
};
/* FME Partial Reconfiguration Control */
UNUSED(feature);
}
+static int fme_err_check_seu(struct feature_fme_err *fme_err)
+{
+ struct feature_fme_error_capability error_cap;
+
+ error_cap.csr = readq(&fme_err->fme_err_capability);
+
+ return error_cap.seu_support ? 1 : 0;
+}
+
+static int fme_err_get_seu_emr(struct ifpga_fme_hw *fme,
+ u64 *val, bool high)
+{
+ struct feature_fme_err *fme_err
+ = get_fme_feature_ioaddr_by_index(fme,
+ FME_FEATURE_ID_GLOBAL_ERR);
+
+ if (!fme_err_check_seu(fme_err))
+ return -ENODEV;
+
+ if (high)
+ *val = readq(&fme_err->seu_emr_h);
+ else
+ *val = readq(&fme_err->seu_emr_l);
+
+ return 0;
+}
+
static int fme_err_fme_err_get_prop(struct ifpga_feature *feature,
struct feature_prop *prop)
{
return fme_err_get_first_error(fme, &prop->data);
case 0x3: /* NEXT_ERROR */
return fme_err_get_next_error(fme, &prop->data);
+ case 0x5: /* SEU EMR LOW */
+ return fme_err_get_seu_emr(fme, &prop->data, 0);
+ case 0x6: /* SEU EMR HIGH */
+ return fme_err_get_seu_emr(fme, &prop->data, 1);
}
return -ENOENT;
#define FME_ERR_PROP_FIRST_ERROR ERR_PROP_FME_ERR(0x2)
#define FME_ERR_PROP_NEXT_ERROR ERR_PROP_FME_ERR(0x3)
#define FME_ERR_PROP_CLEAR ERR_PROP_FME_ERR(0x4) /* WO */
+#define FME_ERR_PROP_SEU_EMR_LOW ERR_PROP_FME_ERR(0x5)
+#define FME_ERR_PROP_SEU_EMR_HIGH ERR_PROP_FME_ERR(0x6)
#define FME_ERR_PROP_REVISION ERR_PROP_ROOT(0x5)
#define FME_ERR_PROP_PCIE0_ERRORS ERR_PROP_ROOT(0x6) /* RW */
#define FME_ERR_PROP_PCIE1_ERRORS ERR_PROP_ROOT(0x7) /* RW */