enum HNS3_CAPS_BITS caps;
const char *name;
} dev_caps[] = {
- { HNS3_CAPS_UDP_GSO_B, "udp_gso" },
- { HNS3_CAPS_ATR_B, "atr" },
{ HNS3_CAPS_FD_QUEUE_REGION_B, "fd_queue_region" },
{ HNS3_CAPS_PTP_B, "ptp" },
- { HNS3_CAPS_INT_QL_B, "int_ql" },
- { HNS3_CAPS_SIMPLE_BD_B, "simple_bd" },
- { HNS3_CAPS_TX_PUSH_B, "tx_push" },
{ HNS3_CAPS_PHY_IMP_B, "phy_imp" },
{ HNS3_CAPS_TQP_TXRX_INDEP_B, "tqp_txrx_indep" },
{ HNS3_CAPS_HW_PAD_B, "hw_pad" },
{ HNS3_CAPS_STASH_B, "stash" },
{ HNS3_CAPS_UDP_TUNNEL_CSUM_B, "udp_tunnel_csum" },
{ HNS3_CAPS_RAS_IMP_B, "ras_imp" },
- { HNS3_CAPS_FEC_B, "fec" },
- { HNS3_CAPS_PAUSE_B, "pause" },
{ HNS3_CAPS_RXD_ADV_LAYOUT_B, "rxd_adv_layout" }
};
uint32_t i;
{
uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);
- if (hns3_get_bit(caps, HNS3_CAPS_UDP_GSO_B))
- hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_UDP_GSO_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_FD_QUEUE_REGION_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B,
1);
hns3_warn(hw, "ignore PTP capability due to lack of "
"rxd advanced layout capability.");
}
- if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B))
- hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_TQP_TXRX_INDEP_B))
#define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
enum HNS3_CAPS_BITS {
- HNS3_CAPS_UDP_GSO_B,
- HNS3_CAPS_ATR_B,
- HNS3_CAPS_FD_QUEUE_REGION_B,
+ /*
+ * The following capability index definitions must be the same as those
+ * of the firmware.
+ */
+ HNS3_CAPS_FD_QUEUE_REGION_B = 2,
HNS3_CAPS_PTP_B,
- HNS3_CAPS_INT_QL_B,
- HNS3_CAPS_SIMPLE_BD_B,
- HNS3_CAPS_TX_PUSH_B,
- HNS3_CAPS_PHY_IMP_B,
+ HNS3_CAPS_PHY_IMP_B = 7,
HNS3_CAPS_TQP_TXRX_INDEP_B,
HNS3_CAPS_HW_PAD_B,
HNS3_CAPS_STASH_B,
HNS3_CAPS_UDP_TUNNEL_CSUM_B,
HNS3_CAPS_RAS_IMP_B,
- HNS3_CAPS_FEC_B,
- HNS3_CAPS_PAUSE_B,
- HNS3_CAPS_RXD_ADV_LAYOUT_B,
+ HNS3_CAPS_RXD_ADV_LAYOUT_B = 15,
};
enum HNS3_API_CAP_BITS {
#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
-#define HNS3_DEV_SUPPORT_DCB_B 0x0
-#define HNS3_DEV_SUPPORT_COPPER_B 0x1
-#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
-#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
-#define HNS3_DEV_SUPPORT_PTP_B 0x4
-#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
-#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
-#define HNS3_DEV_SUPPORT_STASH_B 0x7
-#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
-#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
-#define HNS3_DEV_SUPPORT_RAS_IMP_B 0xB
+enum {
+ HNS3_DEV_SUPPORT_DCB_B,
+ HNS3_DEV_SUPPORT_COPPER_B,
+ HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B,
+ HNS3_DEV_SUPPORT_PTP_B,
+ HNS3_DEV_SUPPORT_INDEP_TXRX_B,
+ HNS3_DEV_SUPPORT_STASH_B,
+ HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
+ HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,
+ HNS3_DEV_SUPPORT_RAS_IMP_B,
+};
#define hns3_dev_dcb_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
#define hns3_dev_copper_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
-/* Support UDP GSO offload */
-#define hns3_dev_udp_gso_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
-
/* Support the queue region action rule of flow directory */
#define hns3_dev_fd_queue_region_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
#define hns3_dev_ptp_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
-#define hns3_dev_tx_push_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
-
/* Support to Independently enable/disable/reset Tx or Rx queues */
#define hns3_dev_indep_txrx_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)