net/qede/base: add attention bits for AH chip

add attention bits for CHIP_NUM_AH_xxx

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c
index 3d6c2f1..cb719a3 100644 (file)
--- a/drivers/net/qede/base/ecore_int.c
+++ b/drivers/net/qede/base/ecore_int.c
@@ -59,6 +59,11 @@ struct aeu_invert_reg_bit {
 #define ATTENTION_OFFSET_MASK          (0x000ff000)
 #define ATTENTION_OFFSET_SHIFT         (12)
 
+#define ATTENTION_BB_MASK              (0x00700000)
+#define ATTENTION_BB_SHIFT             (20)
+#define ATTENTION_BB(value)            ((value) << ATTENTION_BB_SHIFT)
+#define ATTENTION_BB_DIFFERENT         (1 << 23)
+
 #define        ATTENTION_CLEAR_ENABLE          (1 << 28)
        unsigned int flags;
 
@@ -468,7 +473,26 @@ static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
        return ECORE_INVAL;
 }
 
-/* Notice aeu_invert_reg must be defined in the same order of bits as HW;  */
+/* Instead of major changes to the data-structure, we have a some 'special'
+ * identifiers for sources that changed meaning between adapters.
+ */
+enum aeu_invert_reg_special_type {
+       AEU_INVERT_REG_SPECIAL_CNIG_0,
+       AEU_INVERT_REG_SPECIAL_CNIG_1,
+       AEU_INVERT_REG_SPECIAL_CNIG_2,
+       AEU_INVERT_REG_SPECIAL_CNIG_3,
+       AEU_INVERT_REG_SPECIAL_MAX,
+};
+
+static struct aeu_invert_reg_bit
+aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
+       {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
+       {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
+       {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
+       {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
+};
+
+/* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
        {
         {                      /* After Invert 1 */
@@ -511,8 +535,18 @@ static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
           OSAL_NULL, MAX_BLOCK_ID},
          {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
           ecore_general_attention_35, MAX_BLOCK_ID},
-         {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
-          BLOCK_CNIG},
+         {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
+                        ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
+                        OSAL_NULL, BLOCK_NWS},
+         {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
+                           ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
+                           OSAL_NULL, BLOCK_NWS},
+         {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
+                        ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
+                        OSAL_NULL, BLOCK_NWM},
+         {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
+                           ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
+                           OSAL_NULL, BLOCK_NWM},
          {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
          {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
          {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
@@ -634,6 +668,27 @@ static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 
 };
 
+static struct aeu_invert_reg_bit *
+ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
+                       struct aeu_invert_reg_bit *p_bit)
+{
+       if (!ECORE_IS_BB(p_hwfn->p_dev))
+               return p_bit;
+
+       if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
+               return p_bit;
+
+       return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
+                                 ATTENTION_BB_SHIFT];
+}
+
+static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
+                                    struct aeu_invert_reg_bit *p_bit)
+{
+       return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
+                 ATTENTION_PARITY);
+}
+
 #define ATTN_STATE_BITS                (0xfff)
 #define ATTN_BITS_MASKABLE     (0x3ff)
 struct ecore_sb_attn_info {
@@ -868,7 +923,7 @@ static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
                for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
                        struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
 
-                       if ((p_bit->flags & ATTENTION_PARITY) &&
+                       if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
                            !!(parities & (1 << bit_idx))) {
                                ecore_int_deassertion_parity(p_hwfn, p_bit,
                                                             bit_idx);
@@ -905,15 +960,12 @@ static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
                                unsigned long int bitmask;
                                u8 bit, bit_len;
 
+                               /* Need to account bits with changed meaning */
                                p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
 
-                               /* No need to handle attention-only bits */
-                               if (p_aeu->flags == ATTENTION_PAR)
-                                       continue;
-
                                bit = bit_idx;
                                bit_len = ATTENTION_LENGTH(p_aeu->flags);
-                               if (p_aeu->flags & ATTENTION_PAR) {
+                               if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
                                        /* Skip Parity */
                                        bit++;
                                        bit_len--;
@@ -1215,12 +1267,13 @@ static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
        for (i = 0; i < NUM_ATTN_REGS; i++) {
                /* j is array index, k is bit index */
                for (j = 0, k = 0; k < 32; j++) {
-                       unsigned int flags = aeu_descs[i].bits[j].flags;
+                       struct aeu_invert_reg_bit *p_aeu;
 
-                       if (flags & ATTENTION_PARITY)
+                       p_aeu = &aeu_descs[i].bits[j];
+                       if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
                                sb_info->parity_mask[i] |= 1 << k;
 
-                       k += ATTENTION_LENGTH(flags);
+                       k += ATTENTION_LENGTH(p_aeu->flags);
                }
                DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
                           "Attn Mask [Reg %d]: 0x%08x\n",