common/cnxk: fix shift offset for TL3 length disable

Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE
register to be 24 instead of zero similar to other level SHAPE
registers. Also mask unused bits in adjust value.

Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable")
Cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>

diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 543adf9e56a6c03fe16427679ed5a93044b3e78e..9e80c2a5fe9ad28e73047d5fa4703097e627f60f 100644 (file)
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -642,6 +642,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node,
        else if (profile)
                adjust = profile->pkt_len_adj;
 
+       adjust &= 0x1FF;
        plt_tm_dbg("Shaper config node %s(%u) lvl %u id %u, "
                   "pir %" PRIu64 "(%" PRIu64 "B),"
                   " cir %" PRIu64 "(%" PRIu64 "B)"
@@ -708,7 +709,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node,
                /* Configure RED algo */
                reg[k] = NIX_AF_TL3X_SHAPE(schq);
                regval[k] = (adjust | (uint64_t)node->red_algo << 9 |
-                            (uint64_t)node->pkt_mode);
+                            (uint64_t)node->pkt_mode << 24);
                k++;
 
                break;