]> git.droids-corp.org - dpdk.git/commitdiff
net/txgbe: support OEM subsystem vendor ID
authorJiawen Wu <jiawenwu@trustnetic.com>
Wed, 22 Jun 2022 06:56:07 +0000 (14:56 +0800)
committerFerruh Yigit <ferruh.yigit@xilinx.com>
Wed, 22 Jun 2022 10:32:41 +0000 (12:32 +0200)
Add support for OEM subsystem vendor ID.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
doc/guides/rel_notes/release_22_07.rst
drivers/net/txgbe/base/txgbe_hw.c
drivers/net/txgbe/base/txgbe_hw.h
drivers/net/txgbe/base/txgbe_type.h
drivers/net/txgbe/txgbe_ethdev.c

index 97d1a7d945487ac2d251387713a0b26bff52b02c..5c0743afd84d5ef1755ec7634b881d6bc96bd1f5 100644 (file)
@@ -177,6 +177,10 @@ New Features
 
   * Added support for yt8531s PHY.
 
+* **Updated Wangxun txgbe driver.**
+
+  * Added support for OEM subsystem vendor ID.
+
 * **Added Elliptic Curve Diffie-Hellman (ECDH) algorithm in cryptodev.**
 
   Added support for Elliptic Curve Diffie Hellman (ECDH) asymmetric
index 6a045cba791db08e47039d944725b4749544080e..8966453a03cc62efe03adb79a7287c395162d296 100644 (file)
@@ -2608,6 +2608,45 @@ out:
        return err;
 }
 
+/* cmd_addr is used for some special command:
+ * 1. to be sector address, when implemented erase sector command
+ * 2. to be flash address when implemented read, write flash address
+ *
+ * Return 0 on success, return 1 on failure.
+ */
+u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr)
+{
+       u32 cmd_val, i;
+
+       cmd_val = TXGBE_SPICMD_CMD(cmd) | TXGBE_SPICMD_CLK(3) | cmd_addr;
+       wr32(hw, TXGBE_SPICMD, cmd_val);
+
+       for (i = 0; i < TXGBE_SPI_TIMEOUT; i++) {
+               if (rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_OPDONE)
+                       break;
+
+               usec_delay(10);
+       }
+
+       if (i == TXGBE_SPI_TIMEOUT)
+               return 1;
+
+       return 0;
+}
+
+u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr)
+{
+       u32 status;
+
+       status = txgbe_fmgr_cmd_op(hw, 1, addr);
+       if (status == 0x1) {
+               DEBUGOUT("Read flash timeout.");
+               return status;
+       }
+
+       return rd32(hw, TXGBE_SPIDAT);
+}
+
 /**
  *  txgbe_init_ops_pf - Inits func ptrs and MAC type
  *  @hw: pointer to hardware structure
index fd2f7d784c5014aa4065d63637d498cca61d1ce9..7031589f7cd51b94c3b798788db18257e6a18227 100644 (file)
@@ -111,4 +111,6 @@ s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value);
 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 value);
 s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw);
 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw);
+u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr);
+u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr);
 #endif /* _TXGBE_HW_H_ */
index d95467f9f89cae14a26cd76781fe3282a011b339..343279127f7063e8aad02bea1c333ebd92f98f39 100644 (file)
@@ -28,6 +28,7 @@
 #define TXGBE_FDIR_INIT_DONE_POLL              10
 #define TXGBE_FDIRCMD_CMD_POLL                 10
 #define TXGBE_VF_INIT_TIMEOUT  200 /* Number of retries to clear RSTI */
+#define TXGBE_SPI_TIMEOUT      10000
 
 #define TXGBE_ALIGN            128 /* as intel did */
 
index f0994f028dae21c60915e5c787f7d2f80d597678..dc8c3c70a941eed556d2bcc281597815c480effd 100644 (file)
@@ -594,6 +594,19 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
        /* Vendor and Device ID need to be set before init of shared code */
        hw->device_id = pci_dev->id.device_id;
        hw->vendor_id = pci_dev->id.vendor_id;
+       if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) {
+               hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
+       } else {
+               u32 ssid;
+
+               ssid = txgbe_flash_read_dword(hw, 0xFFFDC);
+               if (ssid == 0x1) {
+                       PMD_INIT_LOG(ERR,
+                               "Read of internal subsystem device id failed\n");
+                       return -ENODEV;
+               }
+               hw->subsystem_device_id = (u16)ssid >> 8 | (u16)ssid << 8;
+       }
        hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
        hw->allow_unsupported_sfp = 1;