#define SFC_EF100_RXQ_NOT_RUNNING 0x2
#define SFC_EF100_RXQ_EXCEPTION 0x4
#define SFC_EF100_RXQ_RSS_HASH 0x10
+#define SFC_EF100_RXQ_USER_MARK 0x20
unsigned int ptr_mask;
unsigned int evq_phase_bit_shift;
unsigned int ready_pkts;
SFC_EF100_RX_PREFIX_FIELD(LENGTH, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(RSS_HASH_VALID, B_FALSE),
+ SFC_EF100_RX_PREFIX_FIELD(USER_FLAG, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(CLASS, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(RSS_HASH, B_FALSE),
+ SFC_EF100_RX_PREFIX_FIELD(USER_MARK, B_FALSE),
#undef SFC_EF100_RX_PREFIX_FIELD
}
ESF_GZ_RX_PREFIX_RSS_HASH);
}
+ if ((rxq->flags & SFC_EF100_RXQ_USER_MARK) &&
+ EFX_TEST_OWORD_BIT(rx_prefix[0], ESF_GZ_RX_PREFIX_USER_FLAG_LBN)) {
+ ol_flags |= PKT_RX_FDIR_ID;
+ /* EFX_OWORD_FIELD converts little-endian to CPU */
+ m->hash.fdir.hi = EFX_OWORD_FIELD(rx_prefix[0],
+ ESF_GZ_RX_PREFIX_USER_MARK);
+ }
+
m->ol_flags = ol_flags;
return true;
}
else
rxq->flags &= ~SFC_EF100_RXQ_RSS_HASH;
+ if ((unsup_rx_prefix_fields &
+ ((1U << EFX_RX_PREFIX_FIELD_USER_FLAG) |
+ (1U << EFX_RX_PREFIX_FIELD_USER_MARK))) == 0)
+ rxq->flags |= SFC_EF100_RXQ_USER_MARK;
+ else
+ rxq->flags &= ~SFC_EF100_RXQ_USER_MARK;
+
rxq->prefix_size = pinfo->erpl_length;
rxq->rearm_data = sfc_ef100_mk_mbuf_rearm_data(rxq->dp.dpq.port_id,
rxq->prefix_size);