net/mlx5: support mbuf fast free offload

This patch adds support of the mbuf fast free offload to the
transmit datapath. This offload allows freeing the mbufs on
transmit completion in the most efficient way. It requires
the all mbufs were allocated from the same pool, have
the reference counter value as 1, and have no any externally
attached buffers.

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
index b0aecb8..ddd131d 100644 (file)
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -9,6 +9,7 @@ Link status          = Y
 Link status event    = Y
 Removal event        = Y
 Rx interrupt         = Y
+Fast mbuf free       = Y
 Queue start/stop     = Y
 Burst mode info      = Y
 MTU update           = Y

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 13fd1d8..1134290 100644 (file)
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -74,6 +74,7 @@ Features
 - RX VLAN stripping.
 - TX VLAN insertion.
 - RX CRC stripping configuration.
+- TX mbuf fast free offload.
 - Promiscuous mode on PF and VF.
 - Multicast promiscuous mode on PF and VF.
 - Hardware checksum offloads.
@@ -353,6 +354,17 @@ Limitations
     for some NICs (such as ConnectX-6 Dx, ConnectX-6 Lx, and BlueField-2).
     The capability bit ``scatter_fcs_w_decap_disable`` shows NIC support.
 
+- TX mbuf fast free:
+
+  - fast free offload assumes the all mbufs being sent are originated from the
+    same memory pool and there is no any extra references to the mbufs (the
+    reference counter for each mbuf is equal 1 on tx_burst call). The latter
+    means there should be no any externally attached buffers in mbufs. It is
+    an application responsibility to provide the correct mbufs if the fast
+    free offload is engaged. The mlx5 PMD implicitly produces the mbufs with
+    externally attached buffers if MPRQ option is enabled, hence, the fast
+    free offload is neither supported nor advertised if there is MPRQ enabled.
+
 - Sample flow:
 
   - Supports ``RTE_FLOW_ACTION_TYPE_SAMPLE`` action only within NIC Rx and E-Switch steering domain.

diff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst
index 82abb3c..c59ef69 100644 (file)
--- a/doc/guides/rel_notes/release_21_02.rst
+++ b/doc/guides/rel_notes/release_21_02.rst
@@ -118,6 +118,7 @@ New Features
     mirroring action on E-Switch.
   * Enlarged the number of flow priorities to 21844 (0 - 21843) for ingress or
     egress flow groups greater than 0 and for any transfer flow group.
+  * Added support for the Tx mbuf fast free offload.
 
 * **Updated Wangxun txgbe driver.**
 

diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 97912dd..2e4b87c 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -1889,6 +1889,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
 /**
  * Free the mbufs from the linear array of pointers.
  *
+ * @param txq
+ *   Pointer to Tx queue structure.
  * @param pkts
  *   Pointer to array of packets to be free.
  * @param pkts_n
@@ -1898,7 +1900,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
  *   compile time and may be used for optimization.
  */
 static __rte_always_inline void
-mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
+mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
+                 struct rte_mbuf **__rte_restrict pkts,
                  unsigned int pkts_n,
                  unsigned int olx __rte_unused)
 {
@@ -1914,6 +1917,16 @@ mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
         */
        MLX5_ASSERT(pkts);
        MLX5_ASSERT(pkts_n);
+       /*
+        * Free mbufs directly to the pool in bulk
+        * if fast free offload is engaged
+        */
+       if (!MLX5_TXOFF_CONFIG(MULTI) && txq->fast_free) {
+               mbuf = *pkts;
+               pool = mbuf->pool;
+               rte_mempool_put_bulk(pool, (void *)pkts, pkts_n);
+               return;
+       }
        for (;;) {
                for (;;) {
                        /*
@@ -1995,11 +2008,12 @@ mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
  * on the tx_burst completion.
  */
 static __rte_noinline void
-__mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
+__mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
+                   struct rte_mbuf **__rte_restrict pkts,
                    unsigned int pkts_n,
                    unsigned int olx __rte_unused)
 {
-       mlx5_tx_free_mbuf(pkts, pkts_n, olx);
+       mlx5_tx_free_mbuf(txq, pkts, pkts_n, olx);
 }
 
 /**
@@ -2033,7 +2047,8 @@ mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
                part = RTE_MIN(part, n_elts);
                MLX5_ASSERT(part);
                MLX5_ASSERT(part <= txq->elts_s);
-               mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
+               mlx5_tx_free_mbuf(txq,
+                                 &txq->elts[txq->elts_tail & txq->elts_m],
                                  part, olx);
                txq->elts_tail += part;
                n_elts -= part;
@@ -5184,7 +5199,7 @@ burst_exit:
        txq->stats.opackets += loc.pkts_sent;
 #endif
        if (MLX5_TXOFF_CONFIG(INLINE) && loc.mbuf_free)
-               __mlx5_tx_free_mbuf(pkts, loc.mbuf_free, olx);
+               __mlx5_tx_free_mbuf(txq, pkts, loc.mbuf_free, olx);
        return loc.pkts_sent;
 }
 
@@ -5829,17 +5844,19 @@ mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 
 int
 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
-                      uint16_t tx_queue_id __rte_unused,
+                      uint16_t tx_queue_id,
                       struct rte_eth_burst_mode *mode)
 {
        eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
+       struct mlx5_priv *priv = dev->data->dev_private;
+       struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
        unsigned int i, olx;
 
        for (i = 0; i < RTE_DIM(txoff_func); i++) {
                if (pkt_burst == txoff_func[i].func) {
                        olx = txoff_func[i].olx;
                        snprintf(mode->info, sizeof(mode->info),
-                                "%s%s%s%s%s%s%s%s%s",
+                                "%s%s%s%s%s%s%s%s%s%s",
                                 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
                                 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
                                 "Legacy MPW" : "Enhanced MPW") : "No MPW",
@@ -5858,7 +5875,9 @@ mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
                                 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
                                 " + METADATA" : "",
                                 (olx & MLX5_TXOFF_CONFIG_TXPP) ?
-                                " + TXPP" : "");
+                                " + TXPP" : "",
+                                (txq && txq->fast_free) ?
+                                " + Fast Free" : "");
                        return 0;
                }
        }

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 9dac408..6432030 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -243,6 +243,7 @@ struct mlx5_txq_data {
        uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
        uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
        uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
+       uint16_t fast_free:1; /* mbuf fast free on Tx is enabled. */
        uint16_t inlen_send; /* Ordinary send data inline size. */
        uint16_t inlen_empw; /* eMPW max packet size to inline. */
        uint16_t inlen_mode; /* Minimal data length to inline. */

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 1562442..cd13eb9 100644 (file)
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -123,6 +123,8 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
                                     DEV_TX_OFFLOAD_GRE_TNL_TSO |
                                     DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
        }
+       if (!config->mprq.enabled)
+               offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
        return offloads;
 }
 
@@ -805,6 +807,10 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
        bool vlan_inline;
        unsigned int temp;
 
+       txq_ctrl->txq.fast_free =
+               !!((txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
+                  !(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) &&
+                  !config->mprq.enabled);
        if (config->txqs_inline == MLX5_ARG_UNSET)
                txqs_inline =
 #if defined(RTE_ARCH_ARM64)