net/ixgbe/base: add missing FDIRSCTPM mask setting

This patch adds missing FDIRSCTPM mask setting for tunneled packets.
It should be set the same way as FDIRTCPM and FDIRUDPM so that SCTP
packets can be filtered correctly.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

diff --git a/drivers/net/ixgbe/base/ixgbe_82599.c b/drivers/net/ixgbe/base/ixgbe_82599.c
index 5bc7c2b..832242e 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_82599.c
+++ b/drivers/net/ixgbe/base/ixgbe_82599.c
@@ -1178,6 +1178,7 @@ mac_reset_top:
        if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
                /* Save the SAN MAC RAR index */
                hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
+
                hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
                                    hw->mac.san_addr, 0, IXGBE_RAH_AV);
 
@@ -1809,14 +1810,23 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
                }
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
 
-               /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
-                * FDIRDIP4M in cloud mode to allow L3/L3 packets to
-                * tunnel.
+               /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
+                * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
+                * L3/L3 packets to tunnel.
                 */
                IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
                IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
+               switch (hw->mac.type) {
+               case ixgbe_mac_X550:
+               case ixgbe_mac_X550EM_x:
+               case ixgbe_mac_X550EM_a:
+                       IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
+                       break;
+               default:
+                       break;
+               }
        }
 
        /* Now mask VM pool and destination IPv6 - bits 5 and 2 */