common/sfc_efx/base: add MAE encap match fields
authorIvan Malov <ivan.malov@oktetlabs.ru>
Tue, 20 Oct 2020 09:13:36 +0000 (10:13 +0100)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 3 Nov 2020 22:24:25 +0000 (23:24 +0100)
Add MCDI-compatible enumeration for these fields and
provide necessary mappings for them to be inserted
directly into mask-value pairs buffer.

These fields are meant to comprise a so-called outer
match specification; provide necessary definitions.

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
drivers/common/sfc_efx/base/efx.h
drivers/common/sfc_efx/base/efx_impl.h
drivers/common/sfc_efx/base/efx_mae.c

index dea1fe3..29ef20f 100644 (file)
@@ -4080,6 +4080,7 @@ efx_mae_get_limits(
 
 typedef enum efx_mae_rule_type_e {
        EFX_MAE_RULE_ACTION = 0,
+       EFX_MAE_RULE_OUTER,
 
        EFX_MAE_RULE_NTYPES
 } efx_mae_rule_type_t;
@@ -4119,6 +4120,22 @@ typedef enum efx_mae_field_id_e {
        EFX_MAE_FIELD_L4_SPORT_BE,
        EFX_MAE_FIELD_L4_DPORT_BE,
        EFX_MAE_FIELD_TCP_FLAGS_BE,
+       EFX_MAE_FIELD_ENC_ETHER_TYPE_BE,
+       EFX_MAE_FIELD_ENC_ETH_SADDR_BE,
+       EFX_MAE_FIELD_ENC_ETH_DADDR_BE,
+       EFX_MAE_FIELD_ENC_VLAN0_TCI_BE,
+       EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE,
+       EFX_MAE_FIELD_ENC_VLAN1_TCI_BE,
+       EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE,
+       EFX_MAE_FIELD_ENC_SRC_IP4_BE,
+       EFX_MAE_FIELD_ENC_DST_IP4_BE,
+       EFX_MAE_FIELD_ENC_IP_PROTO,
+       EFX_MAE_FIELD_ENC_IP_TOS,
+       EFX_MAE_FIELD_ENC_IP_TTL,
+       EFX_MAE_FIELD_ENC_SRC_IP6_BE,
+       EFX_MAE_FIELD_ENC_DST_IP6_BE,
+       EFX_MAE_FIELD_ENC_L4_SPORT_BE,
+       EFX_MAE_FIELD_ENC_L4_DPORT_BE,
 
        EFX_MAE_FIELD_NIDS
 } efx_mae_field_id_t;
index 3d1a4fd..607d3de 100644 (file)
@@ -1698,6 +1698,7 @@ struct efx_mae_match_spec_s {
        uint32_t                        emms_prio;
        union emms_mask_value_pairs {
                uint8_t                 action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
+               uint8_t                 outer[MAE_ENC_FIELD_PAIRS_LEN];
        } emms_mask_value_pairs;
 };
 
index 58b323d..6f32a82 100644 (file)
@@ -267,6 +267,8 @@ efx_mae_match_spec_init(
        efx_rc_t rc;
 
        switch (type) {
+       case EFX_MAE_RULE_OUTER:
+               break;
        case EFX_MAE_RULE_ACTION:
                break;
        default:
@@ -322,6 +324,22 @@ typedef enum efx_mae_field_cap_id_e {
        EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
        EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
        EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
+       EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
+       EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
+       EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
+       EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
+       EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
+       EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
+       EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
+       EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
+       EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
+       EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
+       EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
+       EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
+       EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
+       EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
+       EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
+       EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 
        EFX_MAE_FIELD_CAP_NIDS
 } efx_mae_field_cap_id_t;
@@ -382,6 +400,40 @@ static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
        EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
        EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 
+#undef EFX_MAE_MV_DESC
+};
+
+/* Indices to this array are provided by efx_mae_field_id_t */
+static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
+#define        EFX_MAE_MV_DESC(_name, _endianness)                             \
+       [EFX_MAE_FIELD_##_name] =                                       \
+       {                                                               \
+               EFX_MAE_FIELD_ID_##_name,                               \
+               MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
+               MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
+               MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
+               MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
+               _endianness                                             \
+       }
+
+       EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
+       EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
+       EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
+
 #undef EFX_MAE_MV_DESC
 };
 
@@ -470,6 +522,10 @@ efx_mae_match_spec_field_set(
        }
 
        switch (spec->emms_type) {
+       case EFX_MAE_RULE_OUTER:
+               descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
+               mvp = spec->emms_mask_value_pairs.outer;
+               break;
        case EFX_MAE_RULE_ACTION:
                descp = &__efx_mae_action_rule_mv_desc_set[field_id];
                mvp = spec->emms_mask_value_pairs.action;