* ``Intel QuickAssist Technology C62x``
* ``Intel QuickAssist Technology C3xxx``
* ``Intel QuickAssist Technology D15xx``
+* ``Intel QuickAssist Technology C4xxx``
Features
+-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
| 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | Yes | No |
+-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 3 | C4xxx | p | qat_c4xxx | c4xxx | 18a0 | 1 | 18a1 | 128 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
The ``Driver`` column indicates either the Linux kernel version in which
A new devarg ``phy_mac`` was introduced to allow users to use physical
MAC address of the selected PCAP interface.
+* **Added support for GEN3 devices to Intel QAT driver .**
+
+ Added support for the third generation of Intel QuickAssist devices.
+
* **Updated the QAT PMD.**
The QAT PMD was updated with additional support for:
*/
enum qat_device_gen {
QAT_GEN1 = 1,
- QAT_GEN2
+ QAT_GEN2,
+ QAT_GEN3
};
enum qat_service_type {
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
},
+ [QAT_GEN3] = {
+ .dev_gen = QAT_GEN3,
+ .qp_hw_data = qat_gen3_qps,
+ },
};
{
RTE_PCI_DEVICE(0x8086, 0x6f55),
},
+ {
+ RTE_PCI_DEVICE(0x8086, 0x18a1),
+ },
{.device_id = 0},
};
-
static struct qat_pci_device *
qat_pci_get_dev(uint8_t dev_id)
{
case 0x6f55:
qat_dev->qat_dev_gen = QAT_GEN2;
break;
+ case 0x18a1:
+ qat_dev->qat_dev_gen = QAT_GEN3;
+ break;
default:
QAT_LOG(ERR, "Invalid dev_id, can't determine generation");
return NULL;
}
};
+__extension__
+const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]
+ [ADF_MAX_QPS_ON_ANY_SERVICE] = {
+ /* queue pairs which provide an asymmetric crypto service */
+ [QAT_SERVICE_ASYMMETRIC] = {
+ {
+ .service_type = QAT_SERVICE_ASYMMETRIC,
+ .hw_bundle_num = 0,
+ .tx_ring_num = 0,
+ .rx_ring_num = 4,
+ .tx_msg_size = 64,
+ .rx_msg_size = 32,
+ }
+ },
+ /* queue pairs which provide a symmetric crypto service */
+ [QAT_SERVICE_SYMMETRIC] = {
+ {
+ .service_type = QAT_SERVICE_SYMMETRIC,
+ .hw_bundle_num = 0,
+ .tx_ring_num = 1,
+ .rx_ring_num = 5,
+ .tx_msg_size = 128,
+ .rx_msg_size = 32,
+ }
+ },
+ /* queue pairs which provide a compression service */
+ [QAT_SERVICE_COMPRESSION] = {
+ {
+ .service_type = QAT_SERVICE_COMPRESSION,
+ .hw_bundle_num = 0,
+ .tx_ring_num = 3,
+ .rx_ring_num = 7,
+ .tx_msg_size = 128,
+ .rx_msg_size = 32,
+ }
+ }
+};
+
static int qat_qp_check_queue_alignment(uint64_t phys_addr,
uint32_t queue_size_bytes);
static void qat_queue_delete(struct qat_queue *queue);
} __rte_cache_aligned;
extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
+extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
uint16_t
qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
switch (qat_pci_dev->qat_dev_gen) {
case QAT_GEN1:
case QAT_GEN2:
+ case QAT_GEN3:
comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
break;
default:
internals->qat_dev_capabilities = qat_gen1_sym_capabilities;
break;
case QAT_GEN2:
+ case QAT_GEN3:
internals->qat_dev_capabilities = qat_gen2_sym_capabilities;
break;
default: