EFX_FAMILY_HUNTINGTON,
EFX_FAMILY_MEDFORD,
EFX_FAMILY_MEDFORD2,
+ EFX_FAMILY_RIVERHEAD,
EFX_FAMILY_NTYPES
} efx_family_t;
#define EFX_PCI_VENID_SFC 0x1924
+#define EFX_PCI_VENID_XILINX 0x10EE
#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
#define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
#define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
+#define EFX_PCI_DEVID_RIVERHEAD 0x0100
+#define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
#define EFX_MEM_BAR_SIENA 2
#define EFX_MEM_BAR_MEDFORD2 0
+/* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
+#define EFX_MEM_BAR_RIVERHEAD 2
+
/* Error codes */
(_enp)->en_family == EFX_FAMILY_MEDFORD || \
(_enp)->en_family == EFX_FAMILY_HUNTINGTON)
+#define EFX_FAMILY_IS_EF100(_enp) \
+ ((_enp)->en_family == EFX_FAMILY_RIVERHEAD)
+
#define EFX_NIC_MAGIC 0x02121996
}
}
+ if (venid == EFX_PCI_VENID_XILINX) {
+ switch (devid) {
+#if EFSYS_OPT_RIVERHEAD
+ case EFX_PCI_DEVID_RIVERHEAD:
+ case EFX_PCI_DEVID_RIVERHEAD_VF:
+ *efp = EFX_FAMILY_RIVERHEAD;
+ *membarp = EFX_MEM_BAR_RIVERHEAD;
+ return (0);
+#endif /* EFSYS_OPT_RIVERHEAD */
+ default:
+ break;
+ }
+ }
+
*efp = EFX_FAMILY_INVALID;
return (ENOTSUP);
}