crypto/qat: support AES-GCM J0

This patch adds J0 capability to Intel QuickAssist Technology driver

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h
index 7d216de..27e57aa 100644 (file)
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -227,9 +227,9 @@
                                        .increment = 1                  \
                                },                                      \
                                .iv_size = {                            \
-                                       .min = 12,                      \
+                                       .min = 0,                       \
                                        .max = 12,                      \
-                                       .increment = 0                  \
+                                       .increment = 12                 \
                                },                                      \
                        }, }                                            \
                }, }                                                    \
@@ -252,9 +252,9 @@
                                        .increment = 4                  \
                                },                                      \
                                .iv_size = {                            \
-                                       .min = 12,                      \
+                                       .min = 0,                       \
                                        .max = 12,                      \
-                                       .increment = 0                  \
+                                       .increment = 12                 \
                                }                                       \
                        }, }                                            \
                }, }                                                    \

diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index d8b21bc..61ab9ed 100644 (file)
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -658,6 +658,9 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
        uint8_t key_length = auth_xform->key.length;
        session->aes_cmac = 0;
 
+       session->auth_iv.offset = auth_xform->iv.offset;
+       session->auth_iv.length = auth_xform->iv.length;
+
        switch (auth_xform->algo) {
        case RTE_CRYPTO_AUTH_SHA1_HMAC:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
@@ -689,6 +692,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
                }
                session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
+               if (session->auth_iv.length == 0)
+                       session->auth_iv.length = AES_GCM_J0_LEN;
 
                break;
        case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
@@ -728,9 +733,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
                return -EINVAL;
        }
 
-       session->auth_iv.offset = auth_xform->iv.offset;
-       session->auth_iv.length = auth_xform->iv.length;
-
        if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
                if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
                        session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
@@ -813,6 +815,9 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
                }
                session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
+               if (session->cipher_iv.length == 0)
+                       session->cipher_iv.length = AES_GCM_J0_LEN;
+
                break;
        case RTE_CRYPTO_AEAD_AES_CCM:
                if (qat_sym_validate_aes_key(aead_xform->key.length,

diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h
index 98985d6..5a01c81 100644 (file)
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -20,6 +20,11 @@
 
 #define KASUMI_F8_KEY_MODIFIER_4_BYTES   0x55555555
 
+/*
+ * AES-GCM J0 length
+ */
+#define AES_GCM_J0_LEN 16
+
 /* 3DES key sizes */
 #define QAT_3DES_KEY_SZ_OPT1 24 /* Keys are independent */
 #define QAT_3DES_KEY_SZ_OPT2 16 /* K3=K1 */