mcslock: add MCS queued lock implementation
authorPhil Yang <phil.yang@arm.com>
Fri, 5 Jul 2019 10:27:06 +0000 (18:27 +0800)
committerThomas Monjalon <thomas@monjalon.net>
Sun, 7 Jul 2019 21:45:22 +0000 (23:45 +0200)
If there are multiple threads contending, they all attempt to take the
spinlock lock at the same time once it is released. This results in a
huge amount of processor bus traffic, which is a huge performance
killer. Thus, if we somehow order the lock-takers so that they know who
is next in line for the resource we can vastly reduce the amount of bus
traffic.

This patch added MCS lock library. It provides scalability by spinning
on a CPU/thread local variable which avoids expensive cache bouncings.
It provides fairness by maintaining a list of acquirers and passing the
lock to each CPU/thread in the order they acquired the lock.

Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
MAINTAINERS
doc/api/doxy-api-index.md
doc/guides/rel_notes/release_19_08.rst
lib/librte_eal/common/Makefile
lib/librte_eal/common/include/arch/arm/rte_mcslock.h [new file with mode: 0644]
lib/librte_eal/common/include/arch/ppc_64/rte_mcslock.h [new file with mode: 0644]
lib/librte_eal/common/include/arch/x86/rte_mcslock.h [new file with mode: 0644]
lib/librte_eal/common/include/generic/rte_mcslock.h [new file with mode: 0644]
lib/librte_eal/common/meson.build

index cb76357..49f2aa9 100644 (file)
@@ -223,6 +223,10 @@ M: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
 F: lib/librte_eal/common/include/rte_bitmap.h
 F: app/test/test_bitmap.c
 
+MCSlock - EXPERIMENTAL
+M: Phil Yang <phil.yang@arm.com>
+F: lib/librte_eal/common/include/generic/rte_mcslock.h
+
 Ticketlock
 M: Joyce Kong <joyce.kong@arm.com>
 F: lib/librte_eal/common/include/generic/rte_ticketlock.h
index 715248d..d0e32b1 100644 (file)
@@ -63,6 +63,7 @@ The public API headers are grouped by topics:
 
 - **locks**:
   [atomic]             (@ref rte_atomic.h),
+  [mcslock]            (@ref rte_mcslock.h),
   [rwlock]             (@ref rte_rwlock.h),
   [spinlock]           (@ref rte_spinlock.h),
   [ticketlock]         (@ref rte_ticketlock.h),
index a01712c..defbc5e 100644 (file)
@@ -56,6 +56,13 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Added MCS lock.**
+
+  MCS lock provides scalability by spinning on a CPU/thread local variable
+  which avoids expensive cache bouncings.
+  It provides fairness by maintaining a list of acquirers and passing
+  the lock to each CPU/thread in the order they acquired the lock.
+
 * **Updated the EAL Pseudo-random Number Generator.**
 
   The lrand48()-based rte_rand() function is replaced with a
index 1647af7..a00d4fc 100644 (file)
@@ -21,7 +21,7 @@ INC += rte_reciprocal.h rte_fbarray.h rte_uuid.h
 
 GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h
 GENERIC_INC += rte_memcpy.h rte_cpuflags.h
-GENERIC_INC += rte_spinlock.h rte_rwlock.h rte_ticketlock.h
+GENERIC_INC += rte_mcslock.h rte_spinlock.h rte_rwlock.h rte_ticketlock.h
 GENERIC_INC += rte_vect.h rte_pause.h rte_io.h
 
 # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk
diff --git a/lib/librte_eal/common/include/arch/arm/rte_mcslock.h b/lib/librte_eal/common/include/arch/arm/rte_mcslock.h
new file mode 100644 (file)
index 0000000..dd1fe13
--- /dev/null
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef _RTE_MCSLOCK_ARM_H_
+#define _RTE_MCSLOCK_ARM_H_
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_mcslock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MCSLOCK_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_mcslock.h b/lib/librte_eal/common/include/arch/ppc_64/rte_mcslock.h
new file mode 100644 (file)
index 0000000..c58a6ed
--- /dev/null
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef _RTE_MCSLOCK_PPC_64_H_
+#define _RTE_MCSLOCK_PPC_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_mcslock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MCSLOCK_PPC_64_H_ */
diff --git a/lib/librte_eal/common/include/arch/x86/rte_mcslock.h b/lib/librte_eal/common/include/arch/x86/rte_mcslock.h
new file mode 100644 (file)
index 0000000..a8f041a
--- /dev/null
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef _RTE_MCSLOCK_X86_64_H_
+#define _RTE_MCSLOCK_X86_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_mcslock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MCSLOCK_X86_64_H_ */
diff --git a/lib/librte_eal/common/include/generic/rte_mcslock.h b/lib/librte_eal/common/include/generic/rte_mcslock.h
new file mode 100644 (file)
index 0000000..2bef283
--- /dev/null
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef _RTE_MCSLOCK_H_
+#define _RTE_MCSLOCK_H_
+
+/**
+ * @file
+ *
+ * RTE MCS lock
+ *
+ * This file defines the main data structure and APIs for MCS queued lock.
+ *
+ * The MCS lock (proposed by John M. Mellor-Crummey and Michael L. Scott)
+ * provides scalability by spinning on a CPU/thread local variable which
+ * avoids expensive cache bouncings. It provides fairness by maintaining
+ * a list of acquirers and passing the lock to each CPU/thread in the order
+ * they acquired the lock.
+ */
+
+#include <rte_lcore.h>
+#include <rte_common.h>
+#include <rte_pause.h>
+
+/**
+ * The rte_mcslock_t type.
+ */
+typedef struct rte_mcslock {
+       struct rte_mcslock *next;
+       int locked; /* 1 if the queue locked, 0 otherwise */
+} rte_mcslock_t;
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: This API may change without prior notice
+ *
+ * Take the MCS lock.
+ *
+ * @param msl
+ *   A pointer to the pointer of a MCS lock.
+ *   When the lock is initialized or declared, the msl pointer should be
+ *   set to NULL.
+ * @param me
+ *   A pointer to a new node of MCS lock. Each CPU/thread acquiring the
+ *   lock should use its 'own node'.
+ */
+__rte_experimental
+static inline void
+rte_mcslock_lock(rte_mcslock_t **msl, rte_mcslock_t *me)
+{
+       rte_mcslock_t *prev;
+
+       /* Init me node */
+       __atomic_store_n(&me->locked, 1, __ATOMIC_RELAXED);
+       __atomic_store_n(&me->next, NULL, __ATOMIC_RELAXED);
+
+       /* If the queue is empty, the exchange operation is enough to acquire
+        * the lock. Hence, the exchange operation requires acquire semantics.
+        * The store to me->next above should complete before the node is
+        * visible to other CPUs/threads. Hence, the exchange operation requires
+        * release semantics as well.
+        */
+       prev = __atomic_exchange_n(msl, me, __ATOMIC_ACQ_REL);
+       if (likely(prev == NULL)) {
+               /* Queue was empty, no further action required,
+                * proceed with lock taken.
+                */
+               return;
+       }
+       __atomic_store_n(&prev->next, me, __ATOMIC_RELAXED);
+
+       /* The while-load of me->locked should not move above the previous
+        * store to prev->next. Otherwise it will cause a deadlock. Need a
+        * store-load barrier.
+        */
+       __atomic_thread_fence(__ATOMIC_ACQ_REL);
+       /* If the lock has already been acquired, it first atomically
+        * places the node at the end of the queue and then proceeds
+        * to spin on me->locked until the previous lock holder resets
+        * the me->locked using mcslock_unlock().
+        */
+       while (__atomic_load_n(&me->locked, __ATOMIC_ACQUIRE))
+               rte_pause();
+}
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: This API may change without prior notice
+ *
+ * Release the MCS lock.
+ *
+ * @param msl
+ *   A pointer to the pointer of a MCS lock.
+ * @param me
+ *   A pointer to the node of MCS lock passed in rte_mcslock_lock.
+ */
+__rte_experimental
+static inline void
+rte_mcslock_unlock(rte_mcslock_t **msl, rte_mcslock_t *me)
+{
+       /* Check if there are more nodes in the queue. */
+       if (likely(__atomic_load_n(&me->next, __ATOMIC_RELAXED) == NULL)) {
+               /* No, last member in the queue. */
+               rte_mcslock_t *save_me = __atomic_load_n(&me, __ATOMIC_RELAXED);
+
+               /* Release the lock by setting it to NULL */
+               if (likely(__atomic_compare_exchange_n(msl, &save_me, NULL, 0,
+                               __ATOMIC_RELEASE, __ATOMIC_RELAXED)))
+                       return;
+
+               /* Speculative execution would be allowed to read in the
+                * while-loop first. This has the potential to cause a
+                * deadlock. Need a load barrier.
+                */
+               __atomic_thread_fence(__ATOMIC_ACQUIRE);
+               /* More nodes added to the queue by other CPUs.
+                * Wait until the next pointer is set.
+                */
+               while (__atomic_load_n(&me->next, __ATOMIC_RELAXED) == NULL)
+                       rte_pause();
+       }
+
+       /* Pass lock to next waiter. */
+       __atomic_store_n(&me->next->locked, 0, __ATOMIC_RELEASE);
+}
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: This API may change without prior notice
+ *
+ * Try to take the lock.
+ *
+ * @param msl
+ *   A pointer to the pointer of a MCS lock.
+ * @param me
+ *   A pointer to a new node of MCS lock.
+ * @return
+ *   1 if the lock is successfully taken; 0 otherwise.
+ */
+__rte_experimental
+static inline int
+rte_mcslock_trylock(rte_mcslock_t **msl, rte_mcslock_t *me)
+{
+       /* Init me node */
+       __atomic_store_n(&me->next, NULL, __ATOMIC_RELAXED);
+
+       /* Try to lock */
+       rte_mcslock_t *expected = NULL;
+
+       /* The lock can be taken only when the queue is empty. Hence,
+        * the compare-exchange operation requires acquire semantics.
+        * The store to me->next above should complete before the node
+        * is visible to other CPUs/threads. Hence, the compare-exchange
+        * operation requires release semantics as well.
+        */
+       return __atomic_compare_exchange_n(msl, &expected, me, 0,
+                       __ATOMIC_ACQ_REL, __ATOMIC_RELAXED);
+}
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: This API may change without prior notice
+ *
+ * Test if the lock is taken.
+ *
+ * @param msl
+ *   A pointer to a MCS lock node.
+ * @return
+ *   1 if the lock is currently taken; 0 otherwise.
+ */
+__rte_experimental
+static inline int
+rte_mcslock_is_locked(rte_mcslock_t *msl)
+{
+       return (__atomic_load_n(&msl, __ATOMIC_RELAXED) != NULL);
+}
+
+#endif /* _RTE_MCSLOCK_H_ */
index 58b433b..386577c 100644 (file)
@@ -96,6 +96,7 @@ generic_headers = files(
        'include/generic/rte_cpuflags.h',
        'include/generic/rte_cycles.h',
        'include/generic/rte_io.h',
+       'include/generic/rte_mcslock.h',
        'include/generic/rte_memcpy.h',
        'include/generic/rte_pause.h',
        'include/generic/rte_prefetch.h',