return 0;
}
+int
+rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable)
+{
+ uint16_t old_cmd, cmd;
+
+ if (rte_pci_read_config(dev, &old_cmd, sizeof(old_cmd),
+ RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading PCI command register\n");
+ return -1;
+ }
+
+ if (enable)
+ cmd = old_cmd | RTE_PCI_COMMAND_MASTER;
+ else
+ cmd = old_cmd & ~RTE_PCI_COMMAND_MASTER;
+
+ if (cmd == old_cmd)
+ return 0;
+
+ if (rte_pci_write_config(dev, &cmd, sizeof(cmd),
+ RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in writing PCI command register\n");
+ return -1;
+ }
+
+ return 0;
+}
+
struct rte_pci_bus rte_pci_bus = {
.bus = {
.scan = rte_pci_scan,
__rte_experimental
off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
+/**
+ * Enables/Disables Bus Master for device's PCI command register.
+ *
+ * @param dev
+ * A pointer to rte_pci_device structure.
+ * @param enable
+ * Enable or disable Bus Master.
+ *
+ * @return
+ * 0 on success, -1 on error in PCI config space read/write.
+ */
+__rte_experimental
+int rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable);
+
/**
* Register a PCI driver.
*
global:
rte_pci_find_ext_capability;
+
+ # added in 21.08
+ rte_pci_set_bus_master;
};
#define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
#define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
+#define RTE_PCI_COMMAND 0x04 /* 16 bits */
+
+/* PCI Command Register */
+#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
/* PCI Express capability registers */
#define RTE_PCI_EXP_DEVCTL 8 /* Device Control */