#define DORQ_REG_VF_USAGE_CNT_LIM 0x1009ccUL
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL
+
+#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB 15200
+#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 22000
+#define TSEM_REG_DBG_GPRE_VECT 0x1701410UL
+#define MSEM_REG_DBG_GPRE_VECT 0x1801410UL
+#define USEM_REG_DBG_GPRE_VECT 0x1901410UL
+#define XSEM_REG_DBG_GPRE_VECT 0x1401410UL
+#define YSEM_REG_DBG_GPRE_VECT 0x1501410UL
+#define PSEM_REG_DBG_GPRE_VECT 0x1601410UL
+#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE 0x000748UL
+ #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE (0x1UL << 0)
+ #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE_SHIFT 0
+ #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE (0x1UL << 1)
+ #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE_SHIFT 1
+ #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE (0x1UL << 2)
+ #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE_SHIFT 2
+#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE 0x00074cUL
+ #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE (0x1UL << 0)
+ #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE_SHIFT 0
+ #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE (0x1UL << 1)
+ #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE_SHIFT 1
+#define NWS_REG_NWS_CMU_K2 0x720000UL
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 0x000680UL
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 0x000684UL
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 0x0006c0UL
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 0x0006c4UL
+#define MS_REG_MS_CMU_K2 0x6a4000UL
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL
+#define PHY_PCIE_REG_PHY0_K2 0x620000UL
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL
+#define PHY_PCIE_REG_PHY1_K2 0x624000UL
+#define PCIE_REG_DBG_REPEAT_THRESHOLD_COUNT_K2 0x054364UL
+#define PCIE_REG_DBG_FW_TRIGGER_ENABLE_K2 0x05436cUL
+#define RDIF_REG_DEBUG_ERROR_INFO 0x300400UL
+#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64
+#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64
+#define TDIF_REG_DEBUG_ERROR_INFO 0x310400UL
+#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64
+#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64
+#define SEM_FAST_REG_VFC_STATUS 0x000b4cUL
+ #define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY (0x1UL << 0)
+ #define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY_SHIFT 0
+ #define SEM_FAST_REG_VFC_STATUS_VFC_BUSY (0x1UL << 1)
+ #define SEM_FAST_REG_VFC_STATUS_VFC_BUSY_SHIFT 1
+ #define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING (0x1UL << 2)
+ #define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING_SHIFT 2
+#define RSS_REG_RSS_RAM_DATA_SIZE 4
+#define BRB_REG_BIG_RAM_DATA_SIZE 64
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_1 0x0084c0UL
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_2 0x0084e4UL
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_3 0x008508UL
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_4 0x00852cUL
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_5 0x008550UL
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_6 0x008574UL
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_IGU_OUT_7 0x008598UL
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_NIG 0x0085bcUL
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_NIG_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_PXP 0x0085e0UL
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_PXP_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_MCP_OUT_0 0x008628UL
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR 0x008748UL
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31_SHIFT 31
+#define MISC_REG_AEU_ENABLE1_SYS_KILL 0x008604UL
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0 (0x1UL << 0)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0_SHIFT 0
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1 (0x1UL << 1)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1_SHIFT 1
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2 (0x1UL << 2)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2_SHIFT 2
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3 (0x1UL << 3)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3_SHIFT 3
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4 (0x1UL << 4)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4_SHIFT 4
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5 (0x1UL << 5)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5_SHIFT 5
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6 (0x1UL << 6)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6_SHIFT 6
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO (0x1UL << 7)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO_SHIFT 7
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8 (0x1UL << 8)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8_SHIFT 8
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9 (0x1UL << 9)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9_SHIFT 9
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10 (0x1UL << 10)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10_SHIFT 10
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11 (0x1UL << 11)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11_SHIFT 11
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12 (0x1UL << 12)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12_SHIFT 12
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13 (0x1UL << 13)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13_SHIFT 13
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14 (0x1UL << 14)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14_SHIFT 14
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15 (0x1UL << 15)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15_SHIFT 15
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16 (0x1UL << 16)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16_SHIFT 16
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17 (0x1UL << 17)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17_SHIFT 17
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18 (0x1UL << 18)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18_SHIFT 18
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19 (0x1UL << 19)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19_SHIFT 19
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20 (0x1UL << 20)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20_SHIFT 20
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21 (0x1UL << 21)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21_SHIFT 21
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22 (0x1UL << 22)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22_SHIFT 22
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23 (0x1UL << 23)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23_SHIFT 23
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24 (0x1UL << 24)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24_SHIFT 24
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25 (0x1UL << 25)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25_SHIFT 25
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26 (0x1UL << 26)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26_SHIFT 26
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27 (0x1UL << 27)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27_SHIFT 27
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28 (0x1UL << 28)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28_SHIFT 28
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29 (0x1UL << 29)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29_SHIFT 29
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30 (0x1UL << 30)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30_SHIFT 30
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31 (0x1UL << 31)
+ #define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31_SHIFT 31
+#define DBG_REG_FULL_BUFFER_THR 0x01045cUL
+#define MISC_REG_AEU_MASK_ATTN_MCP 0x008498UL
+#define MISC_REG_AEU_SYS_KILL_BEHAVIOR 0x008800UL
+#define MISC_REG_AEU_GENERAL_MASK 0x008828UL
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK (0x1UL << 0)
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK_SHIFT 0
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK (0x1UL << 1)
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK_SHIFT 1
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK (0x1UL << 2)
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK_SHIFT 2
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK (0x1UL << 3)
+ #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK_SHIFT 3
git.droids-corp.org / dpdk.git / commitdiff