net/cnxk: allow zero UDP6 checksum for non-inline device
authorSrujana Challa <schalla@marvell.com>
Fri, 1 Oct 2021 13:40:19 +0000 (19:10 +0530)
committerJerin Jacob <jerinj@marvell.com>
Sat, 2 Oct 2021 13:45:28 +0000 (15:45 +0200)
Sets IP6_UDP_OPT in NIX RX config to allow optional
UDP checksum for IPv6 in case of security offload.
Also disable drop_re when inline inbound is enabled.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
drivers/net/cnxk/cn10k_ethdev.c
drivers/net/cnxk/cnxk_ethdev.c
drivers/net/cnxk/cnxk_ethdev.h

index fa2343c..9dfea99 100644 (file)
@@ -553,6 +553,11 @@ cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 
        dev = cnxk_eth_pmd_priv(eth_dev);
 
+       /* DROP_RE is not supported with inline IPSec for CN10K A0 */
+       if (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() ||
+           roc_model_is_cnf10kb_a0())
+               dev->ipsecd_drop_re_dis = 1;
+
        /* Register up msg callbacks for PTP information */
        roc_nix_ptp_info_cb_register(&dev->nix, cn10k_nix_ptp_info_update_cb);
 
index 5af37d3..03e4e68 100644 (file)
@@ -1021,6 +1021,15 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
                   ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
                   ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
 
+       if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
+               rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
+               /* Disable drop re if rx offload security is enabled and
+                * platform does not support it.
+                */
+               if (dev->ipsecd_drop_re_dis)
+                       rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
+       }
+
        nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
        nb_txq = RTE_MAX(data->nb_tx_queues, 1);
 
index e9784c3..ff21b97 100644 (file)
@@ -269,6 +269,7 @@ struct cnxk_eth_dev {
        union {
                struct {
                        uint64_t cq_min_4k : 1;
+                       uint64_t ipsecd_drop_re_dis : 1;
                };
                uint64_t hwcap;
        };