net/sfc/base: add Medford2 support to NIC module
authorAndy Moreton <amoreton@solarflare.com>
Tue, 20 Feb 2018 07:33:25 +0000 (07:33 +0000)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 30 Mar 2018 12:08:42 +0000 (14:08 +0200)
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
drivers/net/sfc/Makefile
drivers/net/sfc/base/ef10_nic.c
drivers/net/sfc/base/efx.h
drivers/net/sfc/base/efx_impl.h
drivers/net/sfc/base/efx_nic.c
drivers/net/sfc/base/medford2_impl.h [new file with mode: 0644]
drivers/net/sfc/base/medford2_nic.c [new file with mode: 0644]
drivers/net/sfc/base/meson.build

index 8a671dd..32b13dd 100644 (file)
@@ -125,5 +125,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_tx.c
 SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_vpd.c
 SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += hunt_nic.c
 SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += medford_nic.c
+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += medford2_nic.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
index eb9ec2b..311132d 100644 (file)
@@ -10,7 +10,7 @@
 #include "mcdi_mon.h"
 #endif
 
-#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 
 #include "ef10_tlv_layout.h"
 
@@ -25,7 +25,8 @@ efx_mcdi_get_port_assignment(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        (void) memset(payload, 0, sizeof (payload));
        req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
@@ -70,7 +71,8 @@ efx_mcdi_get_port_modes(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        (void) memset(payload, 0, sizeof (payload));
        req.emr_cmd = MC_CMD_GET_PORT_MODES;
@@ -250,7 +252,8 @@ efx_mcdi_get_mac_address_pf(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        (void) memset(payload, 0, sizeof (payload));
        req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
@@ -308,7 +311,8 @@ efx_mcdi_get_mac_address_vf(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        (void) memset(payload, 0, sizeof (payload));
        req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
@@ -372,7 +376,8 @@ efx_mcdi_get_clock(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        (void) memset(payload, 0, sizeof (payload));
        req.emr_cmd = MC_CMD_GET_CLOCK;
@@ -783,7 +788,8 @@ ef10_nic_pio_alloc(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
        EFSYS_ASSERT(bufnump);
        EFSYS_ASSERT(handlep);
        EFSYS_ASSERT(blknump);
@@ -1283,7 +1289,8 @@ ef10_nic_probe(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        /* Read and clear any assertion state */
        if ((rc = efx_mcdi_read_assertion(enp)) != 0)
@@ -1497,7 +1504,8 @@ ef10_nic_init(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        /* Enable reporting of some events (e.g. link change) */
        if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
@@ -1653,7 +1661,8 @@ ef10_nic_get_vi_pool(
        __out           uint32_t *vi_countp)
 {
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        /*
         * Report VIs that the client driver can use.
@@ -1674,7 +1683,8 @@ ef10_nic_get_bar_region(
        efx_rc_t rc;
 
        EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
-                   enp->en_family == EFX_FAMILY_MEDFORD);
+           enp->en_family == EFX_FAMILY_MEDFORD ||
+           enp->en_family == EFX_FAMILY_MEDFORD2);
 
        /*
         * TODO: Specify host memory mapping alignment and granularity
@@ -1771,4 +1781,4 @@ fail1:
 #endif /* EFSYS_OPT_DIAG */
 
 
-#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
+#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
index 1bea124..5135673 100644 (file)
@@ -176,7 +176,7 @@ efx_nic_check_pcie_link_speed(
 
 #if EFSYS_OPT_MCDI
 
-#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 /* Huntington and Medford require MCDIv2 commands */
 #define        WITH_MCDI_V2 1
 #endif
@@ -1144,11 +1144,11 @@ typedef struct efx_nic_cfg_s {
 #if EFSYS_OPT_BIST
        uint32_t                enc_bist_mask;
 #endif /* EFSYS_OPT_BIST */
-#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
        uint32_t                enc_pf;
        uint32_t                enc_vf;
        uint32_t                enc_privilege_mask;
-#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
+#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
        boolean_t               enc_bug26807_workaround;
        boolean_t               enc_bug35388_workaround;
        boolean_t               enc_bug41750_workaround;
index ed685cb..fadcbb4 100644 (file)
 #include "medford_impl.h"
 #endif /* EFSYS_OPT_MEDFORD */
 
-#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
+#if EFSYS_OPT_MEDFORD2
+#include "medford2_impl.h"
+#endif /* EFSYS_OPT_MEDFORD2 */
+
+#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 #include "ef10_impl.h"
-#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
+#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 
 #ifdef __cplusplus
 extern "C" {
@@ -398,9 +402,9 @@ typedef struct efx_filter_s {
 #if EFSYS_OPT_SIENA
        siena_filter_t          *ef_siena_filter;
 #endif /* EFSYS_OPT_SIENA */
-#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
        ef10_filter_table_t     *ef_ef10_filter_table;
-#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
+#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 } efx_filter_t;
 
 #if EFSYS_OPT_SIENA
@@ -683,7 +687,7 @@ struct efx_nic_s {
 #endif /* EFSYS_OPT_SIENA */
                int     enu_unused;
        } en_u;
-#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
+#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
        union en_arch {
                struct {
                        int                     ena_vi_base;
@@ -704,7 +708,7 @@ struct efx_nic_s {
                        size_t                  ena_wc_mem_map_size;
                } ef10;
        } en_arch;
-#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
+#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 };
 
 
@@ -825,6 +829,10 @@ struct efx_txq_s {
                        rev = 'E';                                      \
                        break;                                          \
                                                                        \
+               case EFX_FAMILY_MEDFORD2:                               \
+                       rev = 'F';                                      \
+                       break;                                          \
+                                                                       \
                default:                                                \
                        rev = '?';                                      \
                        break;                                          \
index e318c17..7f32959 100644 (file)
@@ -68,6 +68,24 @@ efx_family(
                        return (0);
 #endif /* EFSYS_OPT_MEDFORD */
 
+#if EFSYS_OPT_MEDFORD2
+               case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
+                       /*
+                        * Hardware default for PF0 of uninitialised Medford2.
+                        * manftest must be able to cope with this device id.
+                        */
+                       *efp = EFX_FAMILY_MEDFORD2;
+                       return (0);
+
+               case EFX_PCI_DEVID_MEDFORD2:
+                       *efp = EFX_FAMILY_MEDFORD2;
+                       return (0);
+
+               case EFX_PCI_DEVID_MEDFORD2_VF:
+                       *efp = EFX_FAMILY_MEDFORD2;
+                       return (0);
+#endif /* EFSYS_OPT_MEDFORD2 */
+
                case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
                default:
                        break;
@@ -135,6 +153,25 @@ static const efx_nic_ops_t __efx_nic_medford_ops = {
 
 #endif /* EFSYS_OPT_MEDFORD */
 
+#if EFSYS_OPT_MEDFORD2
+
+static const efx_nic_ops_t     __efx_nic_medford2_ops = {
+       ef10_nic_probe,                 /* eno_probe */
+       medford2_board_cfg,             /* eno_board_cfg */
+       ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
+       ef10_nic_reset,                 /* eno_reset */
+       ef10_nic_init,                  /* eno_init */
+       ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
+       ef10_nic_get_bar_region,        /* eno_get_bar_region */
+#if EFSYS_OPT_DIAG
+       ef10_nic_register_test,         /* eno_register_test */
+#endif /* EFSYS_OPT_DIAG */
+       ef10_nic_fini,                  /* eno_fini */
+       ef10_nic_unprobe,               /* eno_unprobe */
+};
+
+#endif /* EFSYS_OPT_MEDFORD2 */
+
 
        __checkReturn   efx_rc_t
 efx_nic_create(
@@ -213,6 +250,22 @@ efx_nic_create(
                break;
 #endif /* EFSYS_OPT_MEDFORD */
 
+#if EFSYS_OPT_MEDFORD2
+       case EFX_FAMILY_MEDFORD2:
+               enp->en_enop = &__efx_nic_medford2_ops;
+               enp->en_features =
+                   EFX_FEATURE_IPV6 |
+                   EFX_FEATURE_LINK_EVENTS |
+                   EFX_FEATURE_PERIODIC_MAC_STATS |
+                   EFX_FEATURE_MCDI |
+                   EFX_FEATURE_MAC_HEADER_FILTERS |
+                   EFX_FEATURE_MCDI_DMA |
+                   EFX_FEATURE_PIO_BUFFERS |
+                   EFX_FEATURE_FW_ASSISTED_TSO_V2 |
+                   EFX_FEATURE_PACKED_STREAM;
+               break;
+#endif /* EFSYS_OPT_MEDFORD2 */
+
        default:
                rc = ENOTSUP;
                goto fail2;
diff --git a/drivers/net/sfc/base/medford2_impl.h b/drivers/net/sfc/base/medford2_impl.h
new file mode 100644 (file)
index 0000000..6259a70
--- /dev/null
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2015-2018 Solarflare Communications Inc.
+ * All rights reserved.
+ */
+
+#ifndef        _SYS_MEDFORD2_IMPL_H
+#define        _SYS_MEDFORD2_IMPL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifndef        ER_EZ_TX_PIOBUF_SIZE
+#define        ER_EZ_TX_PIOBUF_SIZE    4096
+#endif
+
+
+#define        MEDFORD2_PIOBUF_NBUFS   (16)
+#define        MEDFORD2_PIOBUF_SIZE    (ER_EZ_TX_PIOBUF_SIZE)
+
+#define        MEDFORD2_MIN_PIO_ALLOC_SIZE     (MEDFORD2_PIOBUF_SIZE / 32)
+
+
+extern __checkReturn   efx_rc_t
+medford2_board_cfg(
+       __in            efx_nic_t *enp);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_MEDFORD2_IMPL_H */
diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
new file mode 100644 (file)
index 0000000..68435a0
--- /dev/null
@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2015-2018 Solarflare Communications Inc.
+ * All rights reserved.
+ */
+
+#include "efx.h"
+#include "efx_impl.h"
+
+
+#if EFSYS_OPT_MEDFORD2
+
+static __checkReturn   efx_rc_t
+efx_mcdi_get_rxdp_config(
+       __in            efx_nic_t *enp,
+       __out           uint32_t *end_paddingp)
+{
+       efx_mcdi_req_t req;
+       uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
+                           MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
+       uint32_t end_padding;
+       efx_rc_t rc;
+
+       memset(payload, 0, sizeof (payload));
+       req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
+       req.emr_in_buf = payload;
+       req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
+       req.emr_out_buf = payload;
+       req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
+
+       efx_mcdi_execute(enp, &req);
+       if (req.emr_rc != 0) {
+               rc = req.emr_rc;
+               goto fail1;
+       }
+
+       if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
+                                   GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
+               /* RX DMA end padding is disabled */
+               end_padding = 0;
+       } else {
+               switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
+                                           GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
+               case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
+                       end_padding = 64;
+                       break;
+               case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
+                       end_padding = 128;
+                       break;
+               case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
+                       end_padding = 256;
+                       break;
+               default:
+                       rc = ENOTSUP;
+                       goto fail2;
+               }
+       }
+
+       *end_paddingp = end_padding;
+
+       return (0);
+
+fail2:
+       EFSYS_PROBE(fail2);
+fail1:
+       EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+       return (rc);
+}
+
+static __checkReturn   efx_rc_t
+medford2_nic_get_required_pcie_bandwidth(
+       __in            efx_nic_t *enp,
+       __out           uint32_t *bandwidth_mbpsp)
+{
+       uint32_t port_modes;
+       uint32_t current_mode;
+       uint32_t bandwidth;
+       efx_rc_t rc;
+
+       /* FIXME: support new Medford2 dynamic port modes */
+
+       if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
+                                   &current_mode)) != 0) {
+               /* No port mode info available. */
+               bandwidth = 0;
+               goto out;
+       }
+
+       if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
+                                                   &bandwidth)) != 0)
+               goto fail1;
+
+out:
+       *bandwidth_mbpsp = bandwidth;
+
+       return (0);
+
+fail1:
+       EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+       return (rc);
+}
+
+       __checkReturn   efx_rc_t
+medford2_board_cfg(
+       __in            efx_nic_t *enp)
+{
+       efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+       efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+       uint8_t mac_addr[6] = { 0 };
+       uint32_t board_type = 0;
+       ef10_link_state_t els;
+       efx_port_t *epp = &(enp->en_port);
+       uint32_t port;
+       uint32_t pf;
+       uint32_t vf;
+       uint32_t mask;
+       uint32_t sysclk, dpcpu_clk;
+       uint32_t base, nvec;
+       uint32_t end_padding;
+       uint32_t bandwidth;
+       efx_rc_t rc;
+
+       /*
+        * FIXME: Likely to be incomplete and incorrect.
+        * Parts of this should be shared with Huntington.
+        */
+
+       if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
+               goto fail1;
+
+       /*
+        * NOTE: The MCDI protocol numbers ports from zero.
+        * The common code MCDI interface numbers ports from one.
+        */
+       emip->emi_port = port + 1;
+
+       if ((rc = ef10_external_port_mapping(enp, port,
+                   &encp->enc_external_port)) != 0)
+               goto fail2;
+
+       /*
+        * Get PCIe function number from firmware (used for
+        * per-function privilege and dynamic config info).
+        *  - PCIe PF: pf = PF number, vf = 0xffff.
+        *  - PCIe VF: pf = parent PF, vf = VF number.
+        */
+       if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
+               goto fail3;
+
+       encp->enc_pf = pf;
+       encp->enc_vf = vf;
+
+       /* MAC address for this function */
+       if (EFX_PCI_FUNCTION_IS_PF(encp)) {
+               rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
+#if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
+               /*
+                * Disable static config checking for Medford NICs, ONLY
+                * for manufacturing test and setup at the factory, to
+                * allow the static config to be installed.
+                */
+#else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
+               if ((rc == 0) && (mac_addr[0] & 0x02)) {
+                       /*
+                        * If the static config does not include a global MAC
+                        * address pool then the board may return a locally
+                        * administered MAC address (this should only happen on
+                        * incorrectly programmed boards).
+                        */
+                       rc = EINVAL;
+               }
+#endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
+       } else {
+               rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
+       }
+       if (rc != 0)
+               goto fail4;
+
+       EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
+
+       /* Board configuration */
+       rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
+       if (rc != 0) {
+               /* Unprivileged functions may not be able to read board cfg */
+               if (rc == EACCES)
+                       board_type = 0;
+               else
+                       goto fail5;
+       }
+
+       encp->enc_board_type = board_type;
+       encp->enc_clk_mult = 1; /* not used for Medford2 */
+
+       /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
+       if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
+               goto fail6;
+
+       /* Obtain the default PHY advertised capabilities */
+       if ((rc = ef10_phy_get_link(enp, &els)) != 0)
+               goto fail7;
+       epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
+       epp->ep_adv_cap_mask = els.els_adv_cap_mask;
+
+       /*
+        * Enable firmware workarounds for hardware errata.
+        * Expected responses are:
+        *  - 0 (zero):
+        *      Success: workaround enabled or disabled as requested.
+        *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
+        *      Firmware does not support the MC_CMD_WORKAROUND request.
+        *      (assume that the workaround is not supported).
+        *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
+        *      Firmware does not support the requested workaround.
+        *  - MC_CMD_ERR_EPERM  (reported as EACCES):
+        *      Unprivileged function cannot enable/disable workarounds.
+        *
+        * See efx_mcdi_request_errcode() for MCDI error translations.
+        */
+
+
+       if (EFX_PCI_FUNCTION_IS_VF(encp)) {
+               /*
+                * Interrupt testing does not work for VFs. See bug50084.
+                * FIXME: Does this still apply to Medford2?
+                */
+               encp->enc_bug41750_workaround = B_TRUE;
+       }
+
+       /* Chained multicast is always enabled on Medford2 */
+       encp->enc_bug26807_workaround = B_TRUE;
+
+       /*
+        * If the bug61265 workaround is enabled, then interrupt holdoff timers
+        * cannot be controlled by timer table writes, so MCDI must be used
+        * (timer table writes can still be used for wakeup timers).
+        */
+       rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
+           NULL);
+       if ((rc == 0) || (rc == EACCES))
+               encp->enc_bug61265_workaround = B_TRUE;
+       else if ((rc == ENOTSUP) || (rc == ENOENT))
+               encp->enc_bug61265_workaround = B_FALSE;
+       else
+               goto fail8;
+
+       /* Get clock frequencies (in MHz). */
+       if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
+               goto fail9;
+
+       /*
+        * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
+        * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
+        */
+       encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
+       encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
+                   FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
+
+       /* Check capabilities of running datapath firmware */
+       if ((rc = ef10_get_datapath_caps(enp)) != 0)
+               goto fail10;
+
+       /* Alignment for receive packet DMA buffers */
+       encp->enc_rx_buf_align_start = 1;
+
+       /* Get the RX DMA end padding alignment configuration */
+       if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
+               if (rc != EACCES)
+                       goto fail11;
+
+               /* Assume largest tail padding size supported by hardware */
+               end_padding = 256;
+       }
+       encp->enc_rx_buf_align_end = end_padding;
+
+       /* Alignment for WPTR updates */
+       encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
+
+       /*
+        * Maximum number of exclusive RSS contexts which can be allocated. The
+        * hardware supports 64, but 6 are reserved for shared contexts. They
+        * are a global resource so not all may be available.
+        */
+       encp->enc_rx_scale_max_exclusive_contexts = 58;
+
+       encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
+       /* No boundary crossing limits */
+       encp->enc_tx_dma_desc_boundary = 0;
+
+       /*
+        * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
+        * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
+        * resources (allocated to this PCIe function), which is zero until
+        * after we have allocated VIs.
+        */
+       encp->enc_evq_limit = 1024;
+       encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
+       encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
+
+       /*
+        * The maximum supported transmit queue size is 2048. TXQs with 4096
+        * descriptors are not supported as the top bit is used for vfifo
+        * stuffing.
+        */
+       encp->enc_txq_max_ndescs = 2048;
+
+       encp->enc_buftbl_limit = 0xFFFFFFFF;
+
+       encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
+       encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
+       encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
+
+       /*
+        * Get the current privilege mask. Note that this may be modified
+        * dynamically, so this value is informational only. DO NOT use
+        * the privilege mask to check for sufficient privileges, as that
+        * can result in time-of-check/time-of-use bugs.
+        */
+       if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
+               goto fail12;
+       encp->enc_privilege_mask = mask;
+
+       /* Get interrupt vector limits */
+       if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
+               if (EFX_PCI_FUNCTION_IS_PF(encp))
+                       goto fail13;
+
+               /* Ignore error (cannot query vector limits from a VF). */
+               base = 0;
+               nvec = 1024;
+       }
+       encp->enc_intr_vec_base = base;
+       encp->enc_intr_limit = nvec;
+
+       /*
+        * Maximum number of bytes into the frame the TCP header can start for
+        * firmware assisted TSO to work.
+        */
+       encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
+
+       /*
+        * Medford2 stores a single global copy of VPD, not per-PF as on
+        * Huntington.
+        */
+       encp->enc_vpd_is_global = B_TRUE;
+
+       rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
+       if (rc != 0)
+               goto fail14;
+       encp->enc_required_pcie_bandwidth_mbps = bandwidth;
+       encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
+
+       return (0);
+
+fail14:
+       EFSYS_PROBE(fail14);
+fail13:
+       EFSYS_PROBE(fail13);
+fail12:
+       EFSYS_PROBE(fail12);
+fail11:
+       EFSYS_PROBE(fail11);
+fail10:
+       EFSYS_PROBE(fail10);
+fail9:
+       EFSYS_PROBE(fail9);
+fail8:
+       EFSYS_PROBE(fail8);
+fail7:
+       EFSYS_PROBE(fail7);
+fail6:
+       EFSYS_PROBE(fail6);
+fail5:
+       EFSYS_PROBE(fail5);
+fail4:
+       EFSYS_PROBE(fail4);
+fail3:
+       EFSYS_PROBE(fail3);
+fail2:
+       EFSYS_PROBE(fail2);
+fail1:
+       EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+       return (rc);
+}
+
+#endif /* EFSYS_OPT_MEDFORD2 */
index f1e4973..a67a638 100644 (file)
@@ -44,7 +44,8 @@ sources = [
        'ef10_tx.c',
        'ef10_vpd.c',
        'hunt_nic.c',
-       'medford_nic.c'
+       'medford_nic.c',
+       'medford2_nic.c'
 ]
 
 extra_flags = [