dmadev: add flag for error handling support

Due to HW or driver limitations, not all dmadevs may support full error
handling e.g. safely managing and reporting an invalid address to a copy
operation. The skeleton dmadev, for example, being pure software will
always seg-fault if passed an invalid address. To indicate the
availability of safe error handling by a device, we add a capability
flag for it.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Conor Walsh <conor.walsh@intel.com>
Reviewed-by: Kevin Laatz <kevin.laatz@intel.com>

diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c
index b6647e6..182d32a 100644 (file)
--- a/lib/dmadev/rte_dmadev.c
+++ b/lib/dmadev/rte_dmadev.c
@@ -722,6 +722,7 @@ dma_capability_name(uint64_t capability)
                { RTE_DMA_CAPA_DEV_TO_DEV,  "dev2dev" },
                { RTE_DMA_CAPA_SVA,         "sva"     },
                { RTE_DMA_CAPA_SILENT,      "silent"  },
+               { RTE_DMA_CAPA_HANDLES_ERRORS, "handles_errors" },
                { RTE_DMA_CAPA_OPS_COPY,    "copy"    },
                { RTE_DMA_CAPA_OPS_COPY_SG, "copy_sg" },
                { RTE_DMA_CAPA_OPS_FILL,    "fill"    },

diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h
index bf78748..f5d2301 100644 (file)
--- a/lib/dmadev/rte_dmadev.h
+++ b/lib/dmadev/rte_dmadev.h
@@ -262,6 +262,14 @@ int16_t rte_dma_next_dev(int16_t start_dev_id);
  * @see struct rte_dma_conf::silent_mode
  */
 #define RTE_DMA_CAPA_SILENT             RTE_BIT64(5)
+/** Supports error handling
+ *
+ * With this bit set, invalid input addresses will be reported as operation failures
+ * to the user but other operations can continue.
+ * Without this bit set, invalid data is not handled by either HW or driver, so user
+ * must ensure that all memory addresses are valid and accessible by HW.
+ */
+#define RTE_DMA_CAPA_HANDLES_ERRORS    RTE_BIT64(6)
 /** Support copy operation.
  * This capability start with index of 32, so that it could leave gap between
  * normal capability and ops capability.