ixgbe/base: use mac-dependent values

This patch changes code to use registers offsets stored in mvals table
instead of values defined statically.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

diff --git a/drivers/net/ixgbe/base/ixgbe_82599.c b/drivers/net/ixgbe/base/ixgbe_82599.c
index 19bd17e..2318190 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_82599.c
+++ b/drivers/net/ixgbe/base/ixgbe_82599.c
@@ -378,8 +378,8 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
        mac->max_tx_queues      = IXGBE_82599_MAX_TX_QUEUES;
        mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 
-       mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
-                                  IXGBE_FWSM_MODE_MASK) ? true : false;
+       mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
+                                     & IXGBE_FWSM_MODE_MASK);
 
        hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 

diff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c
index 08754c8..f00a41c 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_common.c
+++ b/drivers/net/ixgbe/base/ixgbe_common.c
@@ -69,7 +69,7 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
 {
        struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
        struct ixgbe_mac_info *mac = &hw->mac;
-       u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        DEBUGFUNC("ixgbe_init_ops_generic");
 
@@ -1034,7 +1034,7 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
        bus->lan_id = bus->func;
 
        /* check for a port swap */
-       reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
+       reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
        if (reg & IXGBE_FACTPS_LFS)
                bus->func ^= 0x1;
 }
@@ -1160,7 +1160,7 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
                 * Check for EEPROM present first.
                 * If not present leave as none
                 */
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                if (eec & IXGBE_EEC_PRES) {
                        eeprom->type = ixgbe_eeprom_spi;
 
@@ -1721,14 +1721,14 @@ STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
                status = IXGBE_ERR_SWFW_SYNC;
 
        if (status == IXGBE_SUCCESS) {
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
                /* Request EEPROM Access */
                eec |= IXGBE_EEC_REQ;
-               IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+               IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
 
                for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
-                       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+                       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                        if (eec & IXGBE_EEC_GNT)
                                break;
                        usec_delay(5);
@@ -1737,7 +1737,7 @@ STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
                /* Release if grant not acquired */
                if (!(eec & IXGBE_EEC_GNT)) {
                        eec &= ~IXGBE_EEC_REQ;
-                       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
                        DEBUGOUT("Could not acquire EEPROM grant\n");
 
                        hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
@@ -1748,7 +1748,7 @@ STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
                if (status == IXGBE_SUCCESS) {
                        /* Clear CS and SK */
                        eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
-                       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
                        IXGBE_WRITE_FLUSH(hw);
                        usec_delay(1);
                }
@@ -1778,7 +1778,7 @@ STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
                 * If the SMBI bit is 0 when we read it, then the bit will be
                 * set and we have the semaphore
                 */
-               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                if (!(swsm & IXGBE_SWSM_SMBI)) {
                        status = IXGBE_SUCCESS;
                        break;
@@ -1803,7 +1803,7 @@ STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
                 * If the SMBI bit is 0 when we read it, then the bit will be
                 * set and we have the semaphore
                 */
-               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                if (!(swsm & IXGBE_SWSM_SMBI))
                        status = IXGBE_SUCCESS;
        }
@@ -1811,17 +1811,17 @@ STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
        /* Now get the semaphore between SW/FW through the SWESMBI bit */
        if (status == IXGBE_SUCCESS) {
                for (i = 0; i < timeout; i++) {
-                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
 
                        /* Set the SW EEPROM semaphore bit to request access */
                        swsm |= IXGBE_SWSM_SWESMBI;
-                       IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+                       IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
 
                        /*
                         * If we set the bit successfully then we got the
                         * semaphore.
                         */
-                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                        if (swsm & IXGBE_SWSM_SWESMBI)
                                break;
 
@@ -1918,15 +1918,15 @@ STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
 
        DEBUGFUNC("ixgbe_standby_eeprom");
 
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        /* Toggle CS to flush commands */
        eec |= IXGBE_EEC_CS;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
        eec &= ~IXGBE_EEC_CS;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
 }
@@ -1946,7 +1946,7 @@ STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
 
        DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
 
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        /*
         * Mask is used to shift "count" bits of "data" out to the EEPROM
@@ -1967,7 +1967,7 @@ STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
                else
                        eec &= ~IXGBE_EEC_DI;
 
-               IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+               IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
                IXGBE_WRITE_FLUSH(hw);
 
                usec_delay(1);
@@ -1984,7 +1984,7 @@ STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
 
        /* We leave the "DI" bit set to "0" when we leave this routine. */
        eec &= ~IXGBE_EEC_DI;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
 }
 
@@ -2007,7 +2007,7 @@ STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
         * the value of the "DO" bit.  During this "shifting in" process the
         * "DI" bit should always be clear.
         */
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
 
@@ -2015,7 +2015,7 @@ STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
                data = data << 1;
                ixgbe_raise_eeprom_clk(hw, &eec);
 
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
                eec &= ~(IXGBE_EEC_DI);
                if (eec & IXGBE_EEC_DO)
@@ -2041,7 +2041,7 @@ STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
         * (setting the SK bit), then delay
         */
        *eec = *eec | IXGBE_EEC_SK;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
 }
@@ -2060,7 +2060,7 @@ STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
         * delay
         */
        *eec = *eec & ~IXGBE_EEC_SK;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
 }
@@ -2075,19 +2075,19 @@ STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
 
        DEBUGFUNC("ixgbe_release_eeprom");
 
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        eec |= IXGBE_EEC_CS;  /* Pull CS high */
        eec &= ~IXGBE_EEC_SK; /* Lower SCK */
 
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
 
        usec_delay(1);
 
        /* Stop requesting EEPROM access */
        eec &= ~IXGBE_EEC_REQ;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
 
        hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 
@@ -4882,7 +4882,7 @@ bool ixgbe_mng_present(struct ixgbe_hw *hw)
        if (hw->mac.type < ixgbe_mac_82599EB)
                return false;
 
-       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
+       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
        fwsm &= IXGBE_FWSM_MODE_MASK;
        return fwsm == IXGBE_FWSM_FW_MODE_PT;
 }
@@ -4897,7 +4897,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
 {
        u32 fwsm, manc, factps;
 
-       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
+       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
        if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
                return false;
 
@@ -4906,7 +4906,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
                return false;
 
        if (hw->mac.type <= ixgbe_mac_X540) {
-               factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
+               factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
                if (factps & IXGBE_FACTPS_MNGCG)
                        return false;
        }

diff --git a/drivers/net/ixgbe/base/ixgbe_x540.c b/drivers/net/ixgbe/base/ixgbe_x540.c
index 4891702..aae0a51 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_x540.c
+++ b/drivers/net/ixgbe/base/ixgbe_x540.c
@@ -137,8 +137,8 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
         * ARC supported; valid only if manageability features are
         * enabled.
         */
-       mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
-                                  IXGBE_FWSM_MODE_MASK) ? true : false;
+       mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
+                                    & IXGBE_FWSM_MODE_MASK);
 
        hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 
@@ -355,7 +355,7 @@ s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
                eeprom->semaphore_delay = 10;
                eeprom->type = ixgbe_flash;
 
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
                                    IXGBE_EEC_SIZE_SHIFT);
                eeprom->word_size = 1 << (eeprom_size +
@@ -680,8 +680,8 @@ s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
                goto out;
        }
 
-       flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+       flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
 
        status = ixgbe_poll_flash_update_done_X540(hw);
        if (status == IXGBE_SUCCESS)
@@ -690,11 +690,11 @@ s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
                DEBUGOUT("Flash update time out\n");
 
        if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
-               flup = IXGBE_READ_REG(hw, IXGBE_EEC);
+               flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
                if (flup & IXGBE_EEC_SEC1VAL) {
                        flup |= IXGBE_EEC_FLUP;
-                       IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+                       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
                }
 
                status = ixgbe_poll_flash_update_done_X540(hw);
@@ -723,7 +723,7 @@ STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
        DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 
        for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
-               reg = IXGBE_READ_REG(hw, IXGBE_EEC);
+               reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                if (reg & IXGBE_EEC_FLUDONE) {
                        status = IXGBE_SUCCESS;
                        break;
@@ -774,10 +774,11 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
                if (ixgbe_get_swfw_sync_semaphore(hw))
                        return IXGBE_ERR_SWFW_SYNC;
 
-               swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+               swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
                if (!(swfw_sync & (fwmask | swmask | hwmask))) {
                        swfw_sync |= swmask;
-                       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+                       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
+                                       swfw_sync);
                        ixgbe_release_swfw_sync_semaphore(hw);
                        msec_delay(5);
                        return IXGBE_SUCCESS;
@@ -804,10 +805,10 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
         */
        if (ixgbe_get_swfw_sync_semaphore(hw))
                return IXGBE_ERR_SWFW_SYNC;
-       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
        if (swfw_sync & (fwmask | hwmask)) {
                swfw_sync |= swmask;
-               IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+               IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
                ixgbe_release_swfw_sync_semaphore(hw);
                msec_delay(5);
                return IXGBE_SUCCESS;
@@ -851,9 +852,9 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
                swmask |= mask & IXGBE_GSSR_I2C_MASK;
        ixgbe_get_swfw_sync_semaphore(hw);
 
-       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
        swfw_sync &= ~swmask;
-       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
 
        ixgbe_release_swfw_sync_semaphore(hw);
        msec_delay(5);
@@ -880,7 +881,7 @@ STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
                 * If the SMBI bit is 0 when we read it, then the bit will be
                 * set and we have the semaphore
                 */
-               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                if (!(swsm & IXGBE_SWSM_SMBI)) {
                        status = IXGBE_SUCCESS;
                        break;
@@ -891,7 +892,7 @@ STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
        /* Now get the semaphore between SW/FW through the REGSMP bit */
        if (status == IXGBE_SUCCESS) {
                for (i = 0; i < timeout; i++) {
-                       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
                        if (!(swsm & IXGBE_SWFW_REGSMP))
                                break;
 
@@ -931,13 +932,13 @@ STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 
        /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 
-       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
        swsm &= ~IXGBE_SWFW_REGSMP;
-       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
+       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
 
-       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
        swsm &= ~IXGBE_SWSM_SMBI;
-       IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+       IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
 
        IXGBE_WRITE_FLUSH(hw);
 }