crypto/qat: add GMAC capability

Added Galois Message Authentication Code (GMAC) capability to
QuickAssist Technology symmetric cryptographic driver.
GMAC is authentication only variant of Galois Counter Mode (GCM)
where all plaintext is provided with AAD pointer only.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 3adb1796c3b285d5f042c881cb5398d22d6aeebd..a8f9074f531cf187eeeffb62ec43fe86fd242874 100644 (file)
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -65,6 +65,7 @@ Hash algorithms:
 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
 * ``RTE_CRYPTO_AUTH_NULL``
 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
 
 
 Limitations

diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index a980f1a586150ed042462a4cbf76ce445310c82b..6114b26559f549b488eae344ea123e143c3761d5 100644 (file)
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -71,6 +71,7 @@ New Features
   * MD5_HMAC algorithm
   * SHA224-HMAC algorithm
   * SHA384-HMAC algorithm
+  * GMAC algorithm
   * KASUMI (F8 and F9) algorithm
   * NULL algorithm
   * C3XXX device

diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index f989cf76629208c96f3de2051fed568aabd1f419..5969ba6f0354d068e824908cbe46e038bdbf17ca 100644 (file)
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -240,6 +240,31 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
                        }, }
                }, }
        },
+       {       /* AES GMAC (AUTH) */
+               .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+               {.sym = {
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+                       {.auth = {
+                               .algo = RTE_CRYPTO_AUTH_AES_GMAC,
+                               .block_size = 16,
+                               .key_size = {
+                                       .min = 16,
+                                       .max = 32,
+                                       .increment = 8
+                               },
+                               .digest_size = {
+                                       .min = 8,
+                                       .max = 16,
+                                       .increment = 4
+                               },
+                               .aad_size = {
+                                       .min = 1,
+                                       .max = 65535,
+                                       .increment = 1
+                               }
+                       }, }
+               }, }
+       },
        {       /* SNOW3G (UIA2) */
                .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
                {.sym = {
@@ -687,6 +712,9 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AUTH_AES_GCM:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
                break;
+       case RTE_CRYPTO_AUTH_AES_GMAC:
+               session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
+               break;
        case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
                break;
@@ -706,7 +734,6 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AUTH_SHA384:
        case RTE_CRYPTO_AUTH_MD5:
        case RTE_CRYPTO_AUTH_AES_CCM:
-       case RTE_CRYPTO_AUTH_AES_GMAC:
        case RTE_CRYPTO_AUTH_AES_CMAC:
        case RTE_CRYPTO_AUTH_AES_CBC_MAC:
        case RTE_CRYPTO_AUTH_ZUC_EIA3:
@@ -983,6 +1010,19 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
                                qat_req->comn_hdr.serv_specif_flags,
                                ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
                }
+               if (op->sym->cipher.data.length == 0) {
+                       /*
+                        * GMAC
+                        */
+                       qat_req->comn_mid.dest_data_addr =
+                               qat_req->comn_mid.src_data_addr =
+                                       op->sym->auth.aad.phys_addr;
+                       auth_param->u1.aad_adr = 0;
+                       auth_param->auth_len = op->sym->auth.aad.length;
+                       auth_param->u2.aad_sz = 0;
+
+               }
+
        }
 
 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX