]> git.droids-corp.org - dpdk.git/commitdiff
drivers/net: advertise no support for keeping flow rules
authorDmitry Kozlyuk <dkozlyuk@nvidia.com>
Tue, 2 Nov 2021 17:01:32 +0000 (19:01 +0200)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 2 Nov 2021 17:59:17 +0000 (18:59 +0100)
When RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP capability bit is zero,
the specified behavior is the same as it had been before
this bit was introduced. Explicitly reset it in all PMDs
supporting rte_flow API in order to attract the attention
of maintainers, who should eventually choose to advertise
the new capability or not. It is already known that
mlx4 and mlx5 will not support this capability.

For RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP
similar action is not performed,
because no PMD except mlx5 supports indirect actions.
Any PMD that starts doing so will anyway have to consider
all relevant API, including this capability.

Suggested-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Somnath Kotur <somnath.kotur@broadcom.com>
Acked-by: Hyong Youb Kim <hyonkim@cisco.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
26 files changed:
drivers/net/bnxt/bnxt_ethdev.c
drivers/net/bnxt/bnxt_reps.c
drivers/net/cnxk/cnxk_ethdev_ops.c
drivers/net/cxgbe/cxgbe_ethdev.c
drivers/net/dpaa2/dpaa2_ethdev.c
drivers/net/e1000/em_ethdev.c
drivers/net/e1000/igb_ethdev.c
drivers/net/enic/enic_ethdev.c
drivers/net/failsafe/failsafe_ops.c
drivers/net/hinic/hinic_pmd_ethdev.c
drivers/net/hns3/hns3_ethdev.c
drivers/net/hns3/hns3_ethdev_vf.c
drivers/net/i40e/i40e_ethdev.c
drivers/net/i40e/i40e_vf_representor.c
drivers/net/iavf/iavf_ethdev.c
drivers/net/ice/ice_dcf_ethdev.c
drivers/net/igc/igc_ethdev.c
drivers/net/ipn3ke/ipn3ke_representor.c
drivers/net/mvpp2/mrvl_ethdev.c
drivers/net/octeontx2/otx2_ethdev_ops.c
drivers/net/qede/qede_ethdev.c
drivers/net/sfc/sfc_ethdev.c
drivers/net/softnic/rte_eth_softnic.c
drivers/net/tap/rte_eth_tap.c
drivers/net/txgbe/txgbe_ethdev.c
drivers/net/txgbe/txgbe_ethdev_vf.c

index c8dad8a7c5f9fe4f42bc7d7c34b3484c5c12431f..257e6b0d6a04541348f152efed476c0162f8bc82 100644 (file)
@@ -1000,6 +1000,7 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
        dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
        dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                             RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        dev_info->default_rxconf = (struct rte_eth_rxconf) {
                .rx_thresh = {
index 92beea35582e455fca891919b96564f71f0055f4..19da24b41d2dcf2613c2ae01d302d77b9ebe3685 100644 (file)
@@ -546,6 +546,7 @@ int bnxt_rep_dev_info_get_op(struct rte_eth_dev *eth_dev,
        dev_info->max_tx_queues = max_rx_rings;
        dev_info->reta_size = bnxt_rss_hash_tbl_size(parent_bp);
        dev_info->hash_key_size = 40;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        /* MTU specifics */
        dev_info->min_mtu = RTE_ETHER_MIN_MTU;
index 67464302653da8897d88b3a68012d3168d96e525..62306b6cd6fb1285431d3293b16ccab99a254373 100644 (file)
@@ -68,6 +68,7 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
        devinfo->speed_capa = dev->speed_capa;
        devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                            RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       devinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
        return 0;
 }
 
index 4758321778d1d6e596d01da028df8a4920dc5dc3..e7ea76180f36caca1315076c3d2c2c2f60f81c93 100644 (file)
@@ -131,6 +131,8 @@ int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
        device_info->max_vfs = adapter->params.arch.vfcount;
        device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 
+       device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
+
        device_info->rx_queue_offload_capa = 0UL;
        device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 
index 73d17f7b3c61bac25b0f96fb907be9793413c1a6..a3706439d5c922c5e423da2a8ab1a6450c7d291b 100644 (file)
@@ -254,6 +254,7 @@ dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
                        RTE_ETH_LINK_SPEED_2_5G |
                        RTE_ETH_LINK_SPEED_10G;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        dev_info->max_hash_mac_addrs = 0;
        dev_info->max_vfs = 0;
index 18fea4e0acf3d23a85613e0435f07e9f5606707e..31c4870086fd98ab11e8c01a4793c099da2bfa8c 100644 (file)
@@ -1101,6 +1101,8 @@ eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
                        RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M |
                        RTE_ETH_LINK_SPEED_1G;
 
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
+
        /* Preferred queue parameters */
        dev_info->default_rxportconf.nb_queues = 1;
        dev_info->default_txportconf.nb_queues = 1;
index ff06575f03a847df46ad8be63ad0afc364ec8a41..d0e2bc981420cd43d12347176358b50757db152f 100644 (file)
@@ -2168,6 +2168,7 @@ eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
        dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
                                    dev_info->tx_queue_offload_capa;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        switch (hw->mac.type) {
        case e1000_82575:
index c8bdaf1a8e79bf88b7966541b30a91f7a82c94b3..163be09809b1ebbea35a84957bc29c02105f2d0c 100644 (file)
@@ -469,6 +469,7 @@ static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
        device_info->rx_offload_capa = enic->rx_offload_capa;
        device_info->tx_offload_capa = enic->tx_offload_capa;
        device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa;
+       device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
        device_info->default_rxconf = (struct rte_eth_rxconf) {
                .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH
        };
index 822883bc2f8e44a63b895173892b5c358f4a22c3..55e21d635c9eff3eb52a402fb169698a33393396 100644 (file)
@@ -1227,6 +1227,7 @@ fs_dev_infos_get(struct rte_eth_dev *dev,
        infos->dev_capa =
                RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       infos->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        FOREACH_SUBDEV_STATE(sdev, i, dev, DEV_PROBED) {
                struct rte_eth_dev_info sub_info;
index 9cabd3e0c1eca3919a095b9c9e26f202d301a5c3..1853511c3b129a1bc92b9c681387568ffb775fde 100644 (file)
@@ -751,6 +751,8 @@ hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
                                RTE_ETH_TX_OFFLOAD_TCP_TSO |
                                RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
 
+       info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
+
        info->hash_key_size = HINIC_RSS_KEY_SIZE;
        info->reta_size = HINIC_RSS_INDIR_SIZE;
        info->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL;
index 56eca03833ebf686925f440e63b527643c24e255..03447c8d4a48292ac664b3945736fee96d9fc909 100644 (file)
@@ -2598,6 +2598,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
        if (hns3_dev_get_support(hw, INDEP_TXRX))
                info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        if (hns3_dev_get_support(hw, PTP))
                info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
index 675db44e854cb87cb1cf8758fb1818450a8ad326..4a0d73fc2900144cc4d2e5cc2cbd6482b0cb2ac7 100644 (file)
@@ -699,6 +699,7 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
        if (hns3_dev_get_support(hw, INDEP_TXRX))
                info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        info->rx_desc_lim = (struct rte_eth_desc_lim) {
                .nb_max = HNS3_MAX_RING_DESC,
index 62e374d19eb81fccbbb5aa34b4667ec0e1027827..9ea5f303ffa5d58e73050f61bc142c33929e389c 100644 (file)
@@ -3750,6 +3750,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->dev_capa =
                RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
                                                sizeof(uint32_t);
index 663c46b91dc5d4a954f960eb58f798ba84281bc2..7f8e81858e421c55ca0ae474e53eb891829e78ef 100644 (file)
@@ -35,6 +35,8 @@ i40e_vf_representor_dev_infos_get(struct rte_eth_dev *ethdev,
        /* get dev info for the vdev */
        dev_info->device = ethdev->device;
 
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
+
        dev_info->max_rx_queues = ethdev->data->nb_rx_queues;
        dev_info->max_tx_queues = ethdev->data->nb_tx_queues;
 
index d2719d33b3c6c25605d15d096e67a085a649db4c..4677c69ae805f6f88a0543b393d99ce5b0e45c5e 100644 (file)
@@ -1056,6 +1056,7 @@ iavf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->reta_size = vf->vf_res->rss_lut_size;
        dev_info->flow_type_rss_offloads = IAVF_RSS_OFFLOAD_ALL;
        dev_info->max_mac_addrs = IAVF_NUM_MACADDR_MAX;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
        dev_info->rx_offload_capa =
                RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
                RTE_ETH_RX_OFFLOAD_QINQ_STRIP |
index 4d9484e99478742a5c4ff3edc618d363a1083de0..d1e675764127dc1836b8af9f0d365653f2ebd8ee 100644 (file)
@@ -663,6 +663,7 @@ ice_dcf_dev_info_get(struct rte_eth_dev *dev,
        dev_info->hash_key_size = hw->vf_res->rss_key_size;
        dev_info->reta_size = hw->vf_res->rss_lut_size;
        dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        dev_info->rx_offload_capa =
                RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
index 8189ad412a0d70684e5b6b2e1abc98077a5f9d45..3e2bf14b94c3c7b34e7e4cb74f26aa893adea966 100644 (file)
@@ -1477,6 +1477,7 @@ eth_igc_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
        dev_info->max_rx_pktlen = MAX_RX_JUMBO_FRAME_SIZE;
        dev_info->max_mac_addrs = hw->mac.rar_entry_count;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
        dev_info->rx_offload_capa = IGC_RX_OFFLOAD_ALL;
        dev_info->tx_offload_capa = IGC_TX_OFFLOAD_ALL;
        dev_info->rx_queue_offload_capa = RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
index 17088585757f5deb29fe7d588c0e3609cc3401ed..de325c7d293d8ed322c93344bada0869a75e1241 100644 (file)
@@ -96,6 +96,7 @@ ipn3ke_rpst_dev_infos_get(struct rte_eth_dev *ethdev,
        dev_info->dev_capa =
                RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        dev_info->switch_info.name = ethdev->device->name;
        dev_info->switch_info.domain_id = rpst->switch_domain_id;
index 25f213bda5e285a47ec02f645561256464653011..9c7fe13f7fa40676c93c82d9f8033cc323d9abef 100644 (file)
@@ -1709,6 +1709,8 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev,
 {
        struct mrvl_priv *priv = dev->data->dev_private;
 
+       info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
+
        info->speed_capa = RTE_ETH_LINK_SPEED_10M |
                           RTE_ETH_LINK_SPEED_100M |
                           RTE_ETH_LINK_SPEED_1G |
index d5caaa326a5a7a0f8641f95ff7f42098dfeae3b6..48781514c38010ba447ef444a2602720f6775af3 100644 (file)
@@ -583,6 +583,7 @@ otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
 
        devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                                RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       devinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        return 0;
 }
index 8ca00e7f6c2c914f4b66f09f26ddb5b66974048e..3e9aaeecd3937d3d134c003ff7dacebfe8287fa6 100644 (file)
@@ -1367,6 +1367,7 @@ qede_dev_info_get(struct rte_eth_dev *eth_dev,
        dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
        dev_info->rx_desc_lim = qede_rx_desc_lim;
        dev_info->tx_desc_lim = qede_tx_desc_lim;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        if (IS_PF(edev))
                dev_info->max_rx_queues = (uint16_t)RTE_MIN(
index 833d833a0408f33d49dbaeed2144b5a9840a447e..6b0a7e6b0cdf7f7a43845772daa947126e51824d 100644 (file)
@@ -186,6 +186,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 
        dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
                             RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        if (mae->status == SFC_MAE_STATUS_SUPPORTED ||
            mae->status == SFC_MAE_STATUS_ADMIN) {
index 3ef33818a9e004c0797bc6b6f78eb5f1c477d468..8c098cad5b6eb9646c0d06f632bc15ae1411af28 100644 (file)
@@ -93,6 +93,7 @@ pmd_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
        dev_info->max_rx_pktlen = UINT32_MAX;
        dev_info->max_rx_queues = UINT16_MAX;
        dev_info->max_tx_queues = UINT16_MAX;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        return 0;
 }
index a9a76581471566c1aa21d02a66c180cfdbfb8041..37ac18f951cf2570ebde39cf79429a1308b7ffef 100644 (file)
@@ -1006,6 +1006,7 @@ tap_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
         * functions together and not in partial combinations
         */
        dev_info->flow_type_rss_offloads = ~TAP_RSS_HF_MASK;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
        return 0;
 }
index fde9914e493fd3362a734f6ea8ac99439cc32117..5c31ba53587a717c6aa31e3c1e8c4118411c249b 100644 (file)
@@ -2597,6 +2597,7 @@ txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->max_vfs = pci_dev->max_vfs;
        dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
        dev_info->vmdq_queue_num = dev_info->max_rx_queues;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
        dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
        dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
                                     dev_info->rx_queue_offload_capa);
index 4dda55b0c27bb7718245b9936491e37f2c545382..67ae69dec30a52a1aabf4cb2256418821a3413fe 100644 (file)
@@ -487,6 +487,7 @@ txgbevf_dev_info_get(struct rte_eth_dev *dev,
        dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
        dev_info->max_vfs = pci_dev->max_vfs;
        dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
+       dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
        dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
        dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
                                     dev_info->rx_queue_offload_capa);